[llvm] [RISCV] Combine vp_strided_load with zero stride to scalar load + splat (PR #97798)

[Craig Topper via llvm-commits]

topperc wrote:

I think @BeMg is looking at doing this in RISCVCodeGenPrepare where we have access to IR's `isKnownNonZero`. We need that to handle the loop vectorized case where we only know the EVL is non-zero because of a branch in the loop preheader.

https://github.com/llvm/llvm-project/pull/97798