[llvm] [RISCV] Combine vp_strided_load with zero stride to scalar load + splat (PR #97798)

[Craig Topper via llvm-commits]

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@@ -17108,6 +17109,35 @@ SDValue RISCVTargetLowering::PerformDAGCombine(SDNode *N,
                               VPSN->getMemOperand(), IndexType);
     break;
   }
+  case ISD::EXPERIMENTAL_VP_STRIDED_LOAD: {
+    if (DCI.isBeforeLegalize())
+      break;
+    auto *Load = cast<VPStridedLoadSDNode>(N);
+    MVT VT = N->getSimpleValueType(0);
+
+    // Combine a zero strided load -> scalar load + splat
+    // The mask must be all ones and the EVL must be known to not be zero
+    if (!DAG.isKnownNeverZero(Load->getVectorLength()) ||
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topperc wrote:

Do the cheaper checks before calling `DAG.isKnownNeverZero` since that's recursive.

https://github.com/llvm/llvm-project/pull/97798