[llvm] [RISCV] Combine vp_strided_load with zero stride to scalar load + splat (PR #97798)

[Luke Lau via llvm-commits]

lukel97 wrote:

> I think @BeMg is looking at doing this in RISCVCodeGenPrepare where we have access to IR's `isKnownNonZero`. We need that to handle the loop vectorized case where we only know the EVL is non-zero because of a branch in the loop preheader.

That seems like a better place. And it looks like RISCVCodeGenPrepare runs after RISCVGatherScatterLowering, so I think it would still work if we emitted `experimental.vp.strided.load` from the latter. I'll leave this for PR for now then

https://github.com/llvm/llvm-project/pull/97798