[llvm] [RISCV] Add scheduling model for Syntacore SCR3 (PR #95427)

[Anton Sidorenko via llvm-commits]

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@@ -0,0 +1,91 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64-unknown-unknown -mcpu=syntacore-scr3-rv64 --iterations=2 < %s | FileCheck %s --check-prefixes=CHECK,RV64
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asi-sc wrote:

> Is there a purpose for having 2 iterations instead of just 1

No strong motivation in having two iterations. Changed to one iteration.

Is there a better name for this test than using the first letter of every instruction in the sequence? Maybe SCR3-alu.s?

Agree, changed.

https://github.com/llvm/llvm-project/pull/95427