[llvm] [MachineLICM] Workaround - apply RegMasks conservatively (PR #95926)

[Pierre van Houtryve via llvm-commits]

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@@ -0,0 +1,49 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
+# RUN: llc -mtriple=aarch64-unknown-linux-gnu -run-pass=greedy,machinelicm -verify-machineinstrs -debug -o - %s | FileCheck %s
+
+# FIXME: Running RA is needed otherwise it runs pre-RA LICM.
+---
+name: test
+tracksRegLiveness: true
+body: |
+  ; CHECK-LABEL: name: test
+  ; CHECK: bb.0:
+  ; CHECK-NEXT:   successors: %bb.1(0x80000000)
+  ; CHECK-NEXT:   liveins: $x0, $w1, $x2
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   B %bb.1
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.1:
+  ; CHECK-NEXT:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
+  ; CHECK-NEXT:   liveins: $x0, $w1, $x2
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   renamable $q11 = MOVIv4i32 2, 8
+  ; CHECK-NEXT:   BL &memset, csr_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit $x0, implicit $w1, implicit $x2, implicit-def $sp, implicit-def $x0
+  ; CHECK-NEXT:   renamable $q10 = MVNIv4i32 4, 0
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Pierre-vh wrote:

>  If you declare a register with two subregs, tablegen does not know (in general) whether those subregs completely cover the register

This does not spark joy

> Yes, I wondered about that, but it makes me a little nervous that it might leave latent bugs on other targets.

I think with how regunitts work, anything that uses regunits could have similar bugs.

I'm wondering if we could implement some simple logic like this:
- Add a flag to registers to tell TableGen that subregs cover the whole register
- If a register has subregs, and:
  - The flag is set: we generate regunits as we do currently.
  - The flag is not set: we generate one additional regunit exclusive for that register to represent the unknown bits of that registers.

So in the case of AArch64, for Qn registers we'd have n more regunits to represent the upper unknown bits.



https://github.com/llvm/llvm-project/pull/95926