[llvm] [MachineLICM] Workaround - apply RegMasks conservatively (PR #95926)

[Jay Foad via llvm-commits]

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@@ -0,0 +1,49 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
+# RUN: llc -mtriple=aarch64-unknown-linux-gnu -run-pass=greedy,machinelicm -verify-machineinstrs -debug -o - %s | FileCheck %s
+
+# FIXME: Running RA is needed otherwise it runs pre-RA LICM.
+---
+name: test
+tracksRegLiveness: true
+body: |
+  ; CHECK-LABEL: name: test
+  ; CHECK: bb.0:
+  ; CHECK-NEXT:   successors: %bb.1(0x80000000)
+  ; CHECK-NEXT:   liveins: $x0, $w1, $x2
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   B %bb.1
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.1:
+  ; CHECK-NEXT:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
+  ; CHECK-NEXT:   liveins: $x0, $w1, $x2
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   renamable $q11 = MOVIv4i32 2, 8
+  ; CHECK-NEXT:   BL &memset, csr_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit $x0, implicit $w1, implicit $x2, implicit-def $sp, implicit-def $x0
+  ; CHECK-NEXT:   renamable $q10 = MVNIv4i32 4, 0
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jayfoad wrote:

> We could perhaps do a targeted fix for AArch64 too

Yes, I wondered about that, but it makes me a little nervous that it might leave latent bugs on other targets.

> Fix regunits calculations

This deserves wider discussion and might be a can of worms. Currently I think tablegen does not have enough information to generate regunits the way we are suggesting. If you declare a register with two subregs, tablegen does not know (in general) whether those subregs completely cover the register, or whether there is some part that is not covered that should have its own regunit. This is related to the fact that tablegen does not reliably know the width of each physical register -- see the shenanigans in MachineVerifier where it tries to guess the width of a register that may be physical: https://github.com/llvm/llvm-project/blob/6efba06123c96fe7d51cfbb0801407dd3d952839/llvm/lib/CodeGen/MachineVerifier.cpp#L2180

Slightly related: previously I have tried to convert MachineBasicBlock::LiveIns to regunits and ran into a problem with regunits for registers that have ad hoc aliases. There is some discussion here: https://github.com/llvm/llvm-project/pull/79831#issuecomment-1943746260

https://github.com/llvm/llvm-project/pull/95926