[llvm] [AMDGPU] Add IsSingle to a few Interp instructions (PR #95984)

Joe Nash via llvm-commits llvm-commits at lists.llvm.org
Tue Jun 18 13:36:07 PDT 2024


https://github.com/Sisyph created https://github.com/llvm/llvm-project/pull/95984

A _e64 suffix should not be printed since these instructions only have one legal encoding length. The absence of the IsSingle flag is hidden by how the string is printed. We could fix it for GFX10 as well, but we shouldn't change the asm output to omit _e64 at this point.
NFC.

>From e3f0277cde8c25d06c576e3f8d503e44eba26d3e Mon Sep 17 00:00:00 2001
From: Joe Nash <joseph.nash at amd.com>
Date: Mon, 17 Jun 2024 11:53:58 -0400
Subject: [PATCH] [AMDGPU] Add IsSingle to a few Interp instructions

A _e64 suffix should not be printed since these instructions only have
one legal encoding length. The absence of the IsSingle flag is hidden by how the
string is printed. We could fix it for GFX10 as well, but we shouldn't change the
asm output to omit _e64 at this point.
NFC.
---
 llvm/lib/Target/AMDGPU/VOP3Instructions.td | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/llvm/lib/Target/AMDGPU/VOP3Instructions.td b/llvm/lib/Target/AMDGPU/VOP3Instructions.td
index 3d93764bd7ca1..8f9a9af5374a4 100644
--- a/llvm/lib/Target/AMDGPU/VOP3Instructions.td
+++ b/llvm/lib/Target/AMDGPU/VOP3Instructions.td
@@ -105,7 +105,7 @@ class getInterp16Ins <bit HasSrc2, bit HasOMod,
 }
 
 class VOP3_INTERP16 <list<ValueType> ArgVT> : VOPProfile<ArgVT> {
-
+  let IsSingle = 1;
   let HasOMod = !ne(DstVT.Value, f16.Value);
   let HasHigh = 1;
 



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