[llvm] [MachineLICM] Fix regression introduced by d4b8b72 (PR #95746)

[Jay Foad via llvm-commits]

jayfoad wrote:

You shouldn't need both `RUsInMask` and `RUsNotInMask`. Suggestion:
```diff
diff --git a/llvm/lib/CodeGen/MachineLICM.cpp b/llvm/lib/CodeGen/MachineLICM.cpp
index 237527a165e8..dd71a9a3fc79 100644
--- a/llvm/lib/CodeGen/MachineLICM.cpp
+++ b/llvm/lib/CodeGen/MachineLICM.cpp
@@ -424,38 +424,33 @@ static bool InstructionStoresToFI(const MachineInstr *MI, int FI) {
 }
 
 static void applyBitsNotInRegMaskToRegUnitsMask(const TargetRegisterInfo &TRI,
                                                 BitVector &RUs,
                                                 const uint32_t *Mask) {
   const unsigned NumRUs = TRI.getNumRegUnits();
-  BitVector RUsInMask(NumRUs);
-  BitVector RUsNotInMask(NumRUs);
+  BitVector ClobberedRUs(NumRUs, true);
   const unsigned NumRegs = TRI.getNumRegs();
   const unsigned MaskWords = (NumRegs + 31) / 32;
   for (unsigned K = 0; K < MaskWords; ++K) {
     uint32_t Word = Mask[K];
     for (unsigned Bit = 0; Bit < 32; ++Bit) {
       const unsigned PhysReg = (K * 32) + Bit;
       if (PhysReg == NumRegs)
         break;
 
       if (!PhysReg)
         continue;
 
-      // Extract the bit and apply it to the appropriate mask.
-      auto &Mask = ((Word >> Bit) & 1) ? RUsInMask : RUsNotInMask;
-      for (MCRegUnitIterator RUI(PhysReg, &TRI); RUI.isValid(); ++RUI)
-        Mask.set(*RUI);
+      if ((Word >> Bit) & 1) {
+        for (MCRegUnitIterator RUI(PhysReg, &TRI); RUI.isValid(); ++RUI)
+          ClobberedRUs.reset(*RUI);
+      }
     }
   }
 
-  // If a RU needs to be set because it's not in the RegMask, only set it
-  // if all registers from that RU are not in the mask either.
-  RUsNotInMask &= RUsInMask.flip();
-
-  RUs |= RUsNotInMask;
+  RUs |= ClobberedRUs;
 }
 
 /// Examine the instruction for potentai LICM candidate. Also
 /// gather register def and frame object update information.
 void MachineLICMBase::ProcessMI(MachineInstr *MI, BitVector &RUDefs,
                                 BitVector &RUClobbers,
```

https://github.com/llvm/llvm-project/pull/95746