[llvm] [DAG] Add legalization handling for AVGCEIL/AVGFLOOR nodes (PR #92096)

[Simon Pilgrim via llvm-commits]

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@@ -4560,8 +4560,15 @@ unsigned SelectionDAG::ComputeNumSignBits(SDValue Op, const APInt &DemandedElts,
     Tmp = ComputeNumSignBits(Op.getOperand(0), DemandedElts, Depth + 1);
     // SRA X, C -> adds C sign bits.
     if (const APInt *ShAmt =
-            getValidMinimumShiftAmountConstant(Op, DemandedElts))
+            getValidMinimumShiftAmountConstant(Op, DemandedElts)) {
       Tmp = std::min<uint64_t>(Tmp + ShAmt->getZExtValue(), VTBits);
+    } else {
+      KnownBits KnownAmt =
+          computeKnownBits(Op.getOperand(1), DemandedElts, Depth + 1);
+      if (KnownAmt.isConstant() && KnownAmt.getConstant().ult(VTBits))
+        Tmp = std::min<uint64_t>(Tmp + KnownAmt.getConstant().getZExtValue(),
+                                 VTBits);
+    }
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RKSimon wrote:

This is proving tricky to pull out - but I've confirmed that it doesn't cause any notable [compile time diff](https://llvm-compile-time-tracker.com/compare.php?from=7630379156ec08c9d7b1ea3c03c09e7dc89ef4ee&to=7a82854b3d28d02d37183ea91f09b1f7343c4bc4&stat=instructions:u) - as we fallback to ComputeKnownBits call which will call computeKnownBits on the shift amount anyway.

https://github.com/llvm/llvm-project/pull/92096