[llvm] [EarlyIfConversion] Fix the logic to determine predictable branch. (PR #92405)
Mikhail Gudim via llvm-commits
llvm-commits at lists.llvm.org
Wed May 22 07:00:40 PDT 2024
https://github.com/mgudim updated https://github.com/llvm/llvm-project/pull/92405
>From 2641ed09f4a48c141865ca4186a951ea03b73827 Mon Sep 17 00:00:00 2001
From: Mikhail Gudim <mgudim at gmail.com>
Date: Thu, 16 May 2024 10:31:38 -0400
Subject: [PATCH 1/2] [EarlyIfConversion] Fix the logic to determine
predictable branch.
Branch is considered predictable when ALL of the operands used to evaluate
condition are loop-invariant.
---
llvm/lib/CodeGen/EarlyIfConversion.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/llvm/lib/CodeGen/EarlyIfConversion.cpp b/llvm/lib/CodeGen/EarlyIfConversion.cpp
index 2a7bee1618deb..2f8729fcbb945 100644
--- a/llvm/lib/CodeGen/EarlyIfConversion.cpp
+++ b/llvm/lib/CodeGen/EarlyIfConversion.cpp
@@ -879,7 +879,7 @@ bool EarlyIfConverter::shouldConvertIf() {
// from a loop-invariant address predictable; we were unable to prove that it
// doesn't alias any of the memory-writes in the loop, but it is likely to
// read to same value multiple times.
- if (CurrentLoop && any_of(IfConv.Cond, [&](MachineOperand &MO) {
+ if (CurrentLoop && all_of(IfConv.Cond, [&](MachineOperand &MO) {
if (!MO.isReg() || !MO.isUse())
return false;
Register Reg = MO.getReg();
>From 0002712aa596925b7b9347da6f83a5676b73e46f Mon Sep 17 00:00:00 2001
From: Mikhail Gudim <mgudim at gmail.com>
Date: Tue, 21 May 2024 19:08:42 -0400
Subject: [PATCH 2/2] updated tests
---
llvm/lib/CodeGen/EarlyIfConversion.cpp | 8 +--
.../CodeGen/PowerPC/expand-foldable-isel.ll | 57 +++++++++----------
.../PowerPC/loop-instr-form-non-inc.ll | 11 +---
3 files changed, 35 insertions(+), 41 deletions(-)
diff --git a/llvm/lib/CodeGen/EarlyIfConversion.cpp b/llvm/lib/CodeGen/EarlyIfConversion.cpp
index 2f8729fcbb945..7409124fb4549 100644
--- a/llvm/lib/CodeGen/EarlyIfConversion.cpp
+++ b/llvm/lib/CodeGen/EarlyIfConversion.cpp
@@ -881,10 +881,10 @@ bool EarlyIfConverter::shouldConvertIf() {
// read to same value multiple times.
if (CurrentLoop && all_of(IfConv.Cond, [&](MachineOperand &MO) {
if (!MO.isReg() || !MO.isUse())
- return false;
+ return true;
Register Reg = MO.getReg();
if (Register::isPhysicalRegister(Reg))
- return false;
+ return true;
MachineInstr *Def = MRI->getVRegDef(Reg);
return CurrentLoop->isLoopInvariant(*Def) ||
@@ -892,10 +892,10 @@ bool EarlyIfConverter::shouldConvertIf() {
if (Op.isImm())
return true;
if (!MO.isReg() || !MO.isUse())
- return false;
+ return true;
Register Reg = MO.getReg();
if (Register::isPhysicalRegister(Reg))
- return false;
+ return true;
MachineInstr *Def = MRI->getVRegDef(Reg);
return CurrentLoop->isLoopInvariant(*Def);
diff --git a/llvm/test/CodeGen/PowerPC/expand-foldable-isel.ll b/llvm/test/CodeGen/PowerPC/expand-foldable-isel.ll
index 8da7519fa6dc7..38445336a7e1c 100644
--- a/llvm/test/CodeGen/PowerPC/expand-foldable-isel.ll
+++ b/llvm/test/CodeGen/PowerPC/expand-foldable-isel.ll
@@ -36,29 +36,24 @@ define void @_ZN3pov6ot_insEPPNS_14ot_node_structEPNS_15ot_block_structEPNS_12ot
; CHECK-GEN-ISEL-TRUE-NEXT: std r0, 80(r1)
; CHECK-GEN-ISEL-TRUE-NEXT: # implicit-def: $x3
; CHECK-GEN-ISEL-TRUE-NEXT: # implicit-def: $r29
-; CHECK-GEN-ISEL-TRUE-NEXT: b .LBB0_2
; CHECK-GEN-ISEL-TRUE-NEXT: .p2align 4
-; CHECK-GEN-ISEL-TRUE-NEXT: .LBB0_1: # %cond.false21.i156
-; CHECK-GEN-ISEL-TRUE-NEXT: #
-; CHECK-GEN-ISEL-TRUE-NEXT: addi r4, r29, 1
-; CHECK-GEN-ISEL-TRUE-NEXT: srawi r4, r4, 1
-; CHECK-GEN-ISEL-TRUE-NEXT: addze r29, r4
-; CHECK-GEN-ISEL-TRUE-NEXT: .LBB0_2: # %while.cond11
+; CHECK-GEN-ISEL-TRUE-NEXT: .LBB0_1: # %while.cond11
; CHECK-GEN-ISEL-TRUE-NEXT: #
; CHECK-GEN-ISEL-TRUE-NEXT: lwz r4, 0(r3)
; CHECK-GEN-ISEL-TRUE-NEXT: cmplwi r4, 0
-; CHECK-GEN-ISEL-TRUE-NEXT: beq cr0, .LBB0_5
-; CHECK-GEN-ISEL-TRUE-NEXT: # %bb.3: # %while.body21
+; CHECK-GEN-ISEL-TRUE-NEXT: beq cr0, .LBB0_3
+; CHECK-GEN-ISEL-TRUE-NEXT: # %bb.2: # %while.body21
; CHECK-GEN-ISEL-TRUE-NEXT: #
; CHECK-GEN-ISEL-TRUE-NEXT: bl ZN3pov10pov_callocEmmPKciS1_pov
; CHECK-GEN-ISEL-TRUE-NEXT: nop
+; CHECK-GEN-ISEL-TRUE-NEXT: addi r4, r29, 1
+; CHECK-GEN-ISEL-TRUE-NEXT: srwi r5, r29, 1
+; CHECK-GEN-ISEL-TRUE-NEXT: srawi r4, r4, 1
; CHECK-GEN-ISEL-TRUE-NEXT: std r3, 0(r3)
-; CHECK-GEN-ISEL-TRUE-NEXT: bc 12, 4*cr5+lt, .LBB0_1
-; CHECK-GEN-ISEL-TRUE-NEXT: # %bb.4: # %cond.true18.i153
-; CHECK-GEN-ISEL-TRUE-NEXT: #
-; CHECK-GEN-ISEL-TRUE-NEXT: srwi r29, r29, 1
-; CHECK-GEN-ISEL-TRUE-NEXT: b .LBB0_2
-; CHECK-GEN-ISEL-TRUE-NEXT: .LBB0_5: # %lor.rhs
+; CHECK-GEN-ISEL-TRUE-NEXT: addze r4, r4
+; CHECK-GEN-ISEL-TRUE-NEXT: isel r29, r4, r5, 4*cr5+lt
+; CHECK-GEN-ISEL-TRUE-NEXT: b .LBB0_1
+; CHECK-GEN-ISEL-TRUE-NEXT: .LBB0_3: # %lor.rhs
; CHECK-GEN-ISEL-TRUE-NEXT: std r30, 16(r3)
; CHECK-GEN-ISEL-TRUE-NEXT: addi r1, r1, 64
; CHECK-GEN-ISEL-TRUE-NEXT: ld r0, 16(r1)
@@ -81,29 +76,33 @@ define void @_ZN3pov6ot_insEPPNS_14ot_node_structEPNS_15ot_block_structEPNS_12ot
; CHECK-NEXT: std r0, 80(r1)
; CHECK-NEXT: # implicit-def: $x3
; CHECK-NEXT: # implicit-def: $r29
-; CHECK-NEXT: b .LBB0_2
; CHECK-NEXT: .p2align 4
-; CHECK-NEXT: .LBB0_1: # %cond.false21.i156
-; CHECK-NEXT: #
-; CHECK-NEXT: addi r4, r29, 1
-; CHECK-NEXT: srawi r4, r4, 1
-; CHECK-NEXT: addze r29, r4
-; CHECK-NEXT: .LBB0_2: # %while.cond11
+; CHECK-NEXT: .LBB0_1: # %while.cond11
; CHECK-NEXT: #
; CHECK-NEXT: lwz r4, 0(r3)
; CHECK-NEXT: cmplwi r4, 0
-; CHECK-NEXT: beq cr0, .LBB0_5
-; CHECK-NEXT: # %bb.3: # %while.body21
+; CHECK-NEXT: beq cr0, .LBB0_6
+; CHECK-NEXT: # %bb.2: # %while.body21
; CHECK-NEXT: #
; CHECK-NEXT: bl ZN3pov10pov_callocEmmPKciS1_pov
; CHECK-NEXT: nop
+; CHECK-NEXT: addi r4, r29, 1
+; CHECK-NEXT: srwi r5, r29, 1
+; CHECK-NEXT: srawi r4, r4, 1
; CHECK-NEXT: std r3, 0(r3)
-; CHECK-NEXT: bc 12, 4*cr5+lt, .LBB0_1
-; CHECK-NEXT: # %bb.4: # %cond.true18.i153
+; CHECK-NEXT: addze r4, r4
+; CHECK-NEXT: bc 12, 4*cr5+lt, .LBB0_4
+; CHECK-NEXT: # %bb.3: # %while.body21
+; CHECK-NEXT: #
+; CHECK-NEXT: ori r29, r5, 0
+; CHECK-NEXT: b .LBB0_5
+; CHECK-NEXT: .LBB0_4: # %while.body21
+; CHECK-NEXT: #
+; CHECK-NEXT: addi r29, r4, 0
+; CHECK-NEXT: .LBB0_5: # %while.body21
; CHECK-NEXT: #
-; CHECK-NEXT: srwi r29, r29, 1
-; CHECK-NEXT: b .LBB0_2
-; CHECK-NEXT: .LBB0_5: # %lor.rhs
+; CHECK-NEXT: b .LBB0_1
+; CHECK-NEXT: .LBB0_6: # %lor.rhs
; CHECK-NEXT: std r30, 16(r3)
; CHECK-NEXT: addi r1, r1, 64
; CHECK-NEXT: ld r0, 16(r1)
diff --git a/llvm/test/CodeGen/PowerPC/loop-instr-form-non-inc.ll b/llvm/test/CodeGen/PowerPC/loop-instr-form-non-inc.ll
index e87d6392c4c7b..93697ec06be2c 100644
--- a/llvm/test/CodeGen/PowerPC/loop-instr-form-non-inc.ll
+++ b/llvm/test/CodeGen/PowerPC/loop-instr-form-non-inc.ll
@@ -11,18 +11,13 @@ define dso_local void @test_no_inc(i32 signext %a) local_unnamed_addr nounwind a
; CHECK-NEXT: li 7, 0
; CHECK-NEXT: andc 4, 3, 4
; CHECK-NEXT: addi 5, 4, 1
-; CHECK-NEXT: b .LBB0_2
; CHECK-NEXT: .p2align 5
-; CHECK-NEXT: .LBB0_1: # %for.cond.cleanup
+; CHECK-NEXT: .LBB0_1: # %for.cond
; CHECK-NEXT: #
+; CHECK-NEXT: add 8, 3, 6
; CHECK-NEXT: stb 7, 0(5)
; CHECK-NEXT: add 5, 5, 4
-; CHECK-NEXT: .LBB0_2: # %for.cond
-; CHECK-NEXT: #
-; CHECK-NEXT: bc 4, 1, .LBB0_1
-; CHECK-NEXT: # %bb.3: # %for.body.preheader
-; CHECK-NEXT: #
-; CHECK-NEXT: add 6, 3, 6
+; CHECK-NEXT: iselgt 6, 8, 6
; CHECK-NEXT: b .LBB0_1
entry:
%cmp10 = icmp sgt i32 %a, 0
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