[llvm] [AArch64] Expand vector ops when NEON and SVE are unavailable. (PR #90833)

[Paul Walker via llvm-commits]

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@@ -3731,8 +3731,10 @@ bool SelectionDAGLegalize::ExpandNode(SDNode *Node) {
   }
   case ISD::SUB: {
     EVT VT = Node->getValueType(0);
-    assert(TLI.isOperationLegalOrCustom(ISD::ADD, VT) &&
-           TLI.isOperationLegalOrCustom(ISD::XOR, VT) &&
+    assert((VT.isFixedLengthVector() || // fixed length ADD can be expanded to
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paulwalker-arm wrote:

To me the assert exists to ensure optimal code, which is to say it doesn't really make sense to convert the sub to an inverted add unless both those operations are in someway legal.  When not the better result would be to just expand the sub.  Which I guess makes the assert a bear trap for the first person that needs the support.

https://github.com/llvm/llvm-project/pull/90833