[llvm] [AArch64] Expand vector ops when NEON and SVE are unavailable. (PR #90833)

[Sander de Smalen via llvm-commits]

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@@ -3731,8 +3731,10 @@ bool SelectionDAGLegalize::ExpandNode(SDNode *Node) {
   }
   case ISD::SUB: {
     EVT VT = Node->getValueType(0);
-    assert(TLI.isOperationLegalOrCustom(ISD::ADD, VT) &&
-           TLI.isOperationLegalOrCustom(ISD::XOR, VT) &&
+    assert((VT.isFixedLengthVector() || // fixed length ADD can be expanded to
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sdesmalen-arm wrote:

That's right. The way the code now works (if you'd ignore the assert) is that it expands a `sub` into a `add` + `xor`. If those are vector operations that also require expansion, they can be expanded further (in a subsequent step) into scalar operations. The assert is trying to match the way the code currently works, which allows the code to be successfully compiled. I figured updating the assert was the most sensible thing to do for now, given that it's not really a common use-case to optimise for.

https://github.com/llvm/llvm-project/pull/90833