[llvm] [GISel][RISCV] Add legalizer & selector support for G_FREEZE. (PR #92744)

[Yingwei Zheng via llvm-commits]

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@@ -1,164 +1,60 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
-; RUN: llc -mtriple=riscv32 -mattr=+f,+v -global-isel -global-isel-abort=1 -verify-machineinstrs < %s 2>&1 | FileCheck %s --check-prefixes=CHECK,RV32
-; RUN: llc -mtriple=riscv64 -mattr=+f,+v -global-isel -global-isel-abort=1 -verify-machineinstrs < %s 2>&1 | FileCheck %s --check-prefixes=CHECK,RV64
+; RUN: llc -mtriple=riscv32 -mattr=+f,+m,+v -global-isel -global-isel-abort=1 -verify-machineinstrs < %s 2>&1 | FileCheck %s --check-prefixes=CHECK,RV32
+; RUN: llc -mtriple=riscv64 -mattr=+f,+m,+v -global-isel -global-isel-abort=1 -verify-machineinstrs < %s 2>&1 | FileCheck %s --check-prefixes=CHECK,RV64
 
-%struct.T = type { i32, i32 }
-
-define i32 @freeze_int() {
+define i32 @freeze_int(i32 %x) {
 ; RV32-LABEL: freeze_int:
 ; RV32:       # %bb.0:
-; RV32-NEXT:    addi sp, sp, -16
-; RV32-NEXT:    .cfi_def_cfa_offset 16
-; RV32-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
-; RV32-NEXT:    .cfi_offset ra, -4
-; RV32-NEXT:    call __mulsi3
-; RV32-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
-; RV32-NEXT:    addi sp, sp, 16
+; RV32-NEXT:    mul a0, a0, a0
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: freeze_int:
 ; RV64:       # %bb.0:
-; RV64-NEXT:    addi sp, sp, -16
-; RV64-NEXT:    .cfi_def_cfa_offset 16
-; RV64-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
-; RV64-NEXT:    .cfi_offset ra, -8
-; RV64-NEXT:    call __muldi3
-; RV64-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
-; RV64-NEXT:    addi sp, sp, 16
+; RV64-NEXT:    mulw a0, a0, a0
 ; RV64-NEXT:    ret
-  %y1 = freeze i32 undef
+  %y1 = freeze i32 %x
   %t1 = mul i32 %y1, %y1
   ret i32 %t1
 }
 
-define i5 @freeze_int2() {
+define i5 @freeze_int2(i5 %x) {
 ; RV32-LABEL: freeze_int2:
 ; RV32:       # %bb.0:
-; RV32-NEXT:    addi sp, sp, -16
-; RV32-NEXT:    .cfi_def_cfa_offset 16
-; RV32-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
-; RV32-NEXT:    .cfi_offset ra, -4
-; RV32-NEXT:    call __mulsi3
-; RV32-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
-; RV32-NEXT:    addi sp, sp, 16
+; RV32-NEXT:    mul a0, a0, a0
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: freeze_int2:
 ; RV64:       # %bb.0:
-; RV64-NEXT:    addi sp, sp, -16
-; RV64-NEXT:    .cfi_def_cfa_offset 16
-; RV64-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
-; RV64-NEXT:    .cfi_offset ra, -8
-; RV64-NEXT:    call __muldi3
-; RV64-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
-; RV64-NEXT:    addi sp, sp, 16
+; RV64-NEXT:    mulw a0, a0, a0
 ; RV64-NEXT:    ret
-  %y1 = freeze i5 undef
+  %y1 = freeze i5 %x
   %t1 = mul i5 %y1, %y1
   ret i5 %t1
 }
 
-define float @freeze_float() {
+define float @freeze_float(float %x) {
 ; CHECK-LABEL: freeze_float:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    fadd.s fa0, fa5, fa5
+; CHECK-NEXT:    fadd.s fa0, fa0, fa0
 ; CHECK-NEXT:    ret
-  %y1 = freeze float undef
+  %y1 = freeze float %x
   %t1 = fadd float %y1, %y1
   ret float %t1
 }
 
-; TODO: Support vector return values.
-; define <2 x i32> @freeze_ivec() {
-;   %y1 = freeze <2 x i32> undef
+; TODO: Support vector calling conv.
+; define <2 x i32> @freeze_ivec(<2 x i32> %x) {
+;   %y1 = freeze <2 x i32> %x
 ;   %t1 = add <2 x i32> %y1, %y1
 ;   ret <2 x i32> %t1
 ; }
 
-define ptr @freeze_ptr() {
+define ptr @freeze_ptr(ptr %x) {
 ; CHECK-LABEL: freeze_ptr:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a0, a0, 4
 ; CHECK-NEXT:    ret
-  %y1 = freeze ptr undef
+  %y1 = freeze ptr %x
   %t1 = getelementptr i8, ptr %y1, i64 4
   ret ptr %t1
 }
-
-define i32 @freeze_struct() {
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dtcxzyw wrote:

Fixed.

https://github.com/llvm/llvm-project/pull/92744