[llvm] [GISel][RISCV] Add legalizer & selector support for G_FREEZE. (PR #92744)
Yingwei Zheng via llvm-commits
llvm-commits at lists.llvm.org
Tue May 21 06:11:32 PDT 2024
https://github.com/dtcxzyw updated https://github.com/llvm/llvm-project/pull/92744
>From 8f9236dcd4510ea82f64b80368594e81f643df5a Mon Sep 17 00:00:00 2001
From: Yingwei Zheng <dtcxzyw2333 at gmail.com>
Date: Mon, 20 May 2024 20:42:09 +0800
Subject: [PATCH 1/4] [GISel][RISCV] Add legalizer & selector support for
G_FREEZE.
---
.../RISCV/GISel/RISCVInstructionSelector.cpp | 1 +
.../Target/RISCV/GISel/RISCVLegalizerInfo.cpp | 3 +-
llvm/test/CodeGen/RISCV/GlobalISel/freeze.ll | 164 ++++++++++++++++++
.../legalizer/legalize-freeze-rv32.mir | 62 +++++++
.../legalizer/legalize-freeze-rv64.mir | 96 ++++++++++
5 files changed, 325 insertions(+), 1 deletion(-)
create mode 100644 llvm/test/CodeGen/RISCV/GlobalISel/freeze.ll
create mode 100644 llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-freeze-rv32.mir
create mode 100644 llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-freeze-rv64.mir
diff --git a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
index 791d364655e56..da8daa573b89b 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
@@ -558,6 +558,7 @@ bool RISCVInstructionSelector::select(MachineInstr &MI) {
case TargetOpcode::G_PTRTOINT:
case TargetOpcode::G_INTTOPTR:
case TargetOpcode::G_TRUNC:
+ case TargetOpcode::G_FREEZE:
return selectCopy(MI, MRI);
case TargetOpcode::G_CONSTANT: {
Register DstReg = MI.getOperand(0).getReg();
diff --git a/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp b/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
index adc68e9ee4a89..c73fe2c6cecbe 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
@@ -227,7 +227,8 @@ RISCVLegalizerInfo::RISCVLegalizerInfo(const RISCVSubtarget &ST)
ConstantActions.widenScalarToNextPow2(0).clampScalar(0, s32, sXLen);
// TODO: transform illegal vector types into legal vector type
- getActionDefinitionsBuilder({G_IMPLICIT_DEF, G_CONSTANT_FOLD_BARRIER})
+ getActionDefinitionsBuilder(
+ {G_IMPLICIT_DEF, G_CONSTANT_FOLD_BARRIER, G_FREEZE})
.legalFor({s32, sXLen, p0})
.legalIf(typeIsLegalBoolVec(0, BoolVecTys, ST))
.legalIf(typeIsLegalIntOrFPVec(0, IntOrFPVecTys, ST))
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/freeze.ll b/llvm/test/CodeGen/RISCV/GlobalISel/freeze.ll
new file mode 100644
index 0000000000000..ebf4a7958e6a9
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/freeze.ll
@@ -0,0 +1,164 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc -mtriple=riscv32 -mattr=+f,+v -global-isel -global-isel-abort=1 -verify-machineinstrs < %s 2>&1 | FileCheck %s --check-prefixes=CHECK,RV32
+; RUN: llc -mtriple=riscv64 -mattr=+f,+v -global-isel -global-isel-abort=1 -verify-machineinstrs < %s 2>&1 | FileCheck %s --check-prefixes=CHECK,RV64
+
+%struct.T = type { i32, i32 }
+
+define i32 @freeze_int() {
+; RV32-LABEL: freeze_int:
+; RV32: # %bb.0:
+; RV32-NEXT: addi sp, sp, -16
+; RV32-NEXT: .cfi_def_cfa_offset 16
+; RV32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32-NEXT: .cfi_offset ra, -4
+; RV32-NEXT: call __mulsi3
+; RV32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32-NEXT: addi sp, sp, 16
+; RV32-NEXT: ret
+;
+; RV64-LABEL: freeze_int:
+; RV64: # %bb.0:
+; RV64-NEXT: addi sp, sp, -16
+; RV64-NEXT: .cfi_def_cfa_offset 16
+; RV64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64-NEXT: .cfi_offset ra, -8
+; RV64-NEXT: call __muldi3
+; RV64-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64-NEXT: addi sp, sp, 16
+; RV64-NEXT: ret
+ %y1 = freeze i32 undef
+ %t1 = mul i32 %y1, %y1
+ ret i32 %t1
+}
+
+define i5 @freeze_int2() {
+; RV32-LABEL: freeze_int2:
+; RV32: # %bb.0:
+; RV32-NEXT: addi sp, sp, -16
+; RV32-NEXT: .cfi_def_cfa_offset 16
+; RV32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32-NEXT: .cfi_offset ra, -4
+; RV32-NEXT: call __mulsi3
+; RV32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32-NEXT: addi sp, sp, 16
+; RV32-NEXT: ret
+;
+; RV64-LABEL: freeze_int2:
+; RV64: # %bb.0:
+; RV64-NEXT: addi sp, sp, -16
+; RV64-NEXT: .cfi_def_cfa_offset 16
+; RV64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64-NEXT: .cfi_offset ra, -8
+; RV64-NEXT: call __muldi3
+; RV64-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64-NEXT: addi sp, sp, 16
+; RV64-NEXT: ret
+ %y1 = freeze i5 undef
+ %t1 = mul i5 %y1, %y1
+ ret i5 %t1
+}
+
+define float @freeze_float() {
+; CHECK-LABEL: freeze_float:
+; CHECK: # %bb.0:
+; CHECK-NEXT: fadd.s fa0, fa5, fa5
+; CHECK-NEXT: ret
+ %y1 = freeze float undef
+ %t1 = fadd float %y1, %y1
+ ret float %t1
+}
+
+; TODO: Support vector return values.
+; define <2 x i32> @freeze_ivec() {
+; %y1 = freeze <2 x i32> undef
+; %t1 = add <2 x i32> %y1, %y1
+; ret <2 x i32> %t1
+; }
+
+define ptr @freeze_ptr() {
+; CHECK-LABEL: freeze_ptr:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi a0, a0, 4
+; CHECK-NEXT: ret
+ %y1 = freeze ptr undef
+ %t1 = getelementptr i8, ptr %y1, i64 4
+ ret ptr %t1
+}
+
+define i32 @freeze_struct() {
+; RV32-LABEL: freeze_struct:
+; RV32: # %bb.0:
+; RV32-NEXT: add a0, a0, a0
+; RV32-NEXT: ret
+;
+; RV64-LABEL: freeze_struct:
+; RV64: # %bb.0:
+; RV64-NEXT: addw a0, a0, a0
+; RV64-NEXT: ret
+ %y1 = freeze %struct.T undef
+ %v1 = extractvalue %struct.T %y1, 0
+ %v2 = extractvalue %struct.T %y1, 1
+ %t1 = add i32 %v1, %v2
+ ret i32 %t1
+}
+
+define i32 @freeze_anonstruct() {
+; RV32-LABEL: freeze_anonstruct:
+; RV32: # %bb.0:
+; RV32-NEXT: add a0, a0, a0
+; RV32-NEXT: ret
+;
+; RV64-LABEL: freeze_anonstruct:
+; RV64: # %bb.0:
+; RV64-NEXT: addw a0, a0, a0
+; RV64-NEXT: ret
+ %y1 = freeze {i32, i32} undef
+ %v1 = extractvalue {i32, i32} %y1, 0
+ %v2 = extractvalue {i32, i32} %y1, 1
+ %t1 = add i32 %v1, %v2
+ ret i32 %t1
+}
+
+define i32 @freeze_anonstruct2() {
+; RV32-LABEL: freeze_anonstruct2:
+; RV32: # %bb.0:
+; RV32-NEXT: lui a0, 16
+; RV32-NEXT: addi a0, a0, -1
+; RV32-NEXT: and a0, a0, a0
+; RV32-NEXT: add a0, a0, a0
+; RV32-NEXT: ret
+;
+; RV64-LABEL: freeze_anonstruct2:
+; RV64: # %bb.0:
+; RV64-NEXT: lui a0, 16
+; RV64-NEXT: addi a0, a0, -1
+; RV64-NEXT: and a0, a0, a0
+; RV64-NEXT: addw a0, a0, a0
+; RV64-NEXT: ret
+ %y1 = freeze {i32, i16} undef
+ %v1 = extractvalue {i32, i16} %y1, 0
+ %v2 = extractvalue {i32, i16} %y1, 1
+ %z2 = zext i16 %v2 to i32
+ %t1 = add i32 %v1, %z2
+ ret i32 %t1
+}
+
+define i64 @freeze_array() {
+; RV32-LABEL: freeze_array:
+; RV32: # %bb.0:
+; RV32-NEXT: add a0, a0, a0
+; RV32-NEXT: sltu a1, a0, a0
+; RV32-NEXT: add a2, a0, a0
+; RV32-NEXT: add a1, a2, a1
+; RV32-NEXT: ret
+;
+; RV64-LABEL: freeze_array:
+; RV64: # %bb.0:
+; RV64-NEXT: add a0, a0, a0
+; RV64-NEXT: ret
+ %y1 = freeze [2 x i64] undef
+ %v1 = extractvalue [2 x i64] %y1, 0
+ %v2 = extractvalue [2 x i64] %y1, 1
+ %t1 = add i64 %v1, %v2
+ ret i64 %t1
+}
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-freeze-rv32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-freeze-rv32.mir
new file mode 100644
index 0000000000000..4217910dc506f
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-freeze-rv32.mir
@@ -0,0 +1,62 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4
+# RUN: llc -mtriple=riscv32 -mattr=+f,+v -run-pass=legalizer %s -o - | FileCheck %s
+---
+name: freeze_i32
+body: |
+ bb.0.entry:
+ ; CHECK-LABEL: name: freeze_i32
+ ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
+ ; CHECK-NEXT: [[FREEZE:%[0-9]+]]:_(s32) = G_FREEZE [[COPY]]
+ ; CHECK-NEXT: $x10 = COPY [[FREEZE]](s32)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %1:_(s32) = COPY $x10
+ %2:_(s32) = G_FREEZE %1
+ $x10 = COPY %2(s32)
+ PseudoRET implicit $x10
+
+...
+---
+name: freeze_f32
+body: |
+ bb.0.entry:
+ ; CHECK-LABEL: name: freeze_f32
+ ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $f10_f
+ ; CHECK-NEXT: [[FREEZE:%[0-9]+]]:_(s32) = G_FREEZE [[COPY]]
+ ; CHECK-NEXT: $f10_f = COPY [[FREEZE]](s32)
+ ; CHECK-NEXT: PseudoRET implicit $f10_f
+ %1:_(s32) = COPY $f10_f
+ %2:_(s32) = G_FREEZE %1
+ $f10_f = COPY %2(s32)
+ PseudoRET implicit $f10_f
+
+...
+---
+name: freeze_nxv2i1
+body: |
+ bb.0.entry:
+ ; CHECK-LABEL: name: freeze_nxv2i1
+ ; CHECK: [[COPY:%[0-9]+]]:_(<vscale x 2 x s1>) = COPY $v8
+ ; CHECK-NEXT: [[FREEZE:%[0-9]+]]:_(<vscale x 2 x s1>) = G_FREEZE [[COPY]]
+ ; CHECK-NEXT: $v8 = COPY [[FREEZE]](<vscale x 2 x s1>)
+ ; CHECK-NEXT: PseudoRET implicit $v8
+ %1:_(<vscale x 2 x s1>) = COPY $v8
+ %2:_(<vscale x 2 x s1>) = G_FREEZE %1
+ $v8 = COPY %2(<vscale x 2 x s1>)
+ PseudoRET implicit $v8
+
+...
+---
+name: freeze_nxv2i32
+body: |
+ bb.0.entry:
+ ; CHECK-LABEL: name: freeze_nxv2i32
+ ; CHECK: [[COPY:%[0-9]+]]:_(<vscale x 2 x s32>) = COPY $v8
+ ; CHECK-NEXT: [[FREEZE:%[0-9]+]]:_(<vscale x 2 x s32>) = G_FREEZE [[COPY]]
+ ; CHECK-NEXT: $v8 = COPY [[FREEZE]](<vscale x 2 x s32>)
+ ; CHECK-NEXT: PseudoRET implicit $v8
+ %1:_(<vscale x 2 x s32>) = COPY $v8
+ %2:_(<vscale x 2 x s32>) = G_FREEZE %1
+ $v8 = COPY %2(<vscale x 2 x s32>)
+ PseudoRET implicit $v8
+
+...
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-freeze-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-freeze-rv64.mir
new file mode 100644
index 0000000000000..355e225915884
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-freeze-rv64.mir
@@ -0,0 +1,96 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4
+# RUN: llc -mtriple=riscv64 -mattr=+f,+v -run-pass=legalizer %s -o - | FileCheck %s
+---
+name: freeze_i32
+body: |
+ bb.0.entry:
+ ; CHECK-LABEL: name: freeze_i32
+ ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
+ ; CHECK-NEXT: [[FREEZE:%[0-9]+]]:_(s32) = G_FREEZE [[TRUNC]]
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[FREEZE]](s32)
+ ; CHECK-NEXT: $x10 = COPY [[ANYEXT]](s64)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %1:_(s64) = COPY $x10
+ %2:_(s32) = G_TRUNC %1(s64)
+ %3:_(s32) = G_FREEZE %2
+ %4:_(s64) = G_ANYEXT %3(s32)
+ $x10 = COPY %4(s64)
+ PseudoRET implicit $x10
+
+...
+---
+name: freeze_f32
+body: |
+ bb.0.entry:
+ ; CHECK-LABEL: name: freeze_f32
+ ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $f10_f
+ ; CHECK-NEXT: [[FREEZE:%[0-9]+]]:_(s32) = G_FREEZE [[COPY]]
+ ; CHECK-NEXT: $f10_f = COPY [[FREEZE]](s32)
+ ; CHECK-NEXT: PseudoRET implicit $f10_f
+ %1:_(s32) = COPY $f10_f
+ %2:_(s32) = G_FREEZE %1
+ $f10_f = COPY %2(s32)
+ PseudoRET implicit $f10_f
+
+...
+---
+name: freeze_i64
+body: |
+ bb.0.entry:
+ ; CHECK-LABEL: name: freeze_i64
+ ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
+ ; CHECK-NEXT: [[FREEZE:%[0-9]+]]:_(s64) = G_FREEZE [[COPY]]
+ ; CHECK-NEXT: $x10 = COPY [[FREEZE]](s64)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %1:_(s64) = COPY $x10
+ %2:_(s64) = G_FREEZE %1
+ $x10 = COPY %2(s64)
+ PseudoRET implicit $x10
+
+...
+---
+name: freeze_nxv2i1
+body: |
+ bb.0.entry:
+ ; CHECK-LABEL: name: freeze_nxv2i1
+ ; CHECK: [[COPY:%[0-9]+]]:_(<vscale x 2 x s1>) = COPY $v8
+ ; CHECK-NEXT: [[FREEZE:%[0-9]+]]:_(<vscale x 2 x s1>) = G_FREEZE [[COPY]]
+ ; CHECK-NEXT: $v8 = COPY [[FREEZE]](<vscale x 2 x s1>)
+ ; CHECK-NEXT: PseudoRET implicit $v8
+ %1:_(<vscale x 2 x s1>) = COPY $v8
+ %2:_(<vscale x 2 x s1>) = G_FREEZE %1
+ $v8 = COPY %2(<vscale x 2 x s1>)
+ PseudoRET implicit $v8
+
+...
+---
+name: freeze_nxv2i32
+body: |
+ bb.0.entry:
+ ; CHECK-LABEL: name: freeze_nxv2i32
+ ; CHECK: [[COPY:%[0-9]+]]:_(<vscale x 2 x s32>) = COPY $v8
+ ; CHECK-NEXT: [[FREEZE:%[0-9]+]]:_(<vscale x 2 x s32>) = G_FREEZE [[COPY]]
+ ; CHECK-NEXT: $v8 = COPY [[FREEZE]](<vscale x 2 x s32>)
+ ; CHECK-NEXT: PseudoRET implicit $v8
+ %1:_(<vscale x 2 x s32>) = COPY $v8
+ %2:_(<vscale x 2 x s32>) = G_FREEZE %1
+ $v8 = COPY %2(<vscale x 2 x s32>)
+ PseudoRET implicit $v8
+
+...
+---
+name: freeze_nxv2i64
+body: |
+ bb.0.entry:
+ ; CHECK-LABEL: name: freeze_nxv2i64
+ ; CHECK: [[COPY:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $v8
+ ; CHECK-NEXT: [[FREEZE:%[0-9]+]]:_(<vscale x 2 x s64>) = G_FREEZE [[COPY]]
+ ; CHECK-NEXT: $v8m2 = COPY [[FREEZE]](<vscale x 2 x s64>)
+ ; CHECK-NEXT: PseudoRET implicit $v8m2
+ %1:_(<vscale x 2 x s64>) = COPY $v8
+ %2:_(<vscale x 2 x s64>) = G_FREEZE %1
+ $v8m2 = COPY %2(<vscale x 2 x s64>)
+ PseudoRET implicit $v8m2
+
+...
>From 234880974cf8843eaa01fae9522aa99bdf1878e1 Mon Sep 17 00:00:00 2001
From: Yingwei Zheng <dtcxzyw2333 at gmail.com>
Date: Mon, 20 May 2024 22:00:23 +0800
Subject: [PATCH 2/4] [GISel][RISCV] Replace undef with arguments in tests.
NFC.
---
llvm/test/CodeGen/RISCV/GlobalISel/freeze.ll | 140 +++----------------
1 file changed, 18 insertions(+), 122 deletions(-)
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/freeze.ll b/llvm/test/CodeGen/RISCV/GlobalISel/freeze.ll
index ebf4a7958e6a9..5b740b1087d00 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/freeze.ll
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/freeze.ll
@@ -1,164 +1,60 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
-; RUN: llc -mtriple=riscv32 -mattr=+f,+v -global-isel -global-isel-abort=1 -verify-machineinstrs < %s 2>&1 | FileCheck %s --check-prefixes=CHECK,RV32
-; RUN: llc -mtriple=riscv64 -mattr=+f,+v -global-isel -global-isel-abort=1 -verify-machineinstrs < %s 2>&1 | FileCheck %s --check-prefixes=CHECK,RV64
+; RUN: llc -mtriple=riscv32 -mattr=+f,+m,+v -global-isel -global-isel-abort=1 -verify-machineinstrs < %s 2>&1 | FileCheck %s --check-prefixes=CHECK,RV32
+; RUN: llc -mtriple=riscv64 -mattr=+f,+m,+v -global-isel -global-isel-abort=1 -verify-machineinstrs < %s 2>&1 | FileCheck %s --check-prefixes=CHECK,RV64
-%struct.T = type { i32, i32 }
-
-define i32 @freeze_int() {
+define i32 @freeze_int(i32 %x) {
; RV32-LABEL: freeze_int:
; RV32: # %bb.0:
-; RV32-NEXT: addi sp, sp, -16
-; RV32-NEXT: .cfi_def_cfa_offset 16
-; RV32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
-; RV32-NEXT: .cfi_offset ra, -4
-; RV32-NEXT: call __mulsi3
-; RV32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
-; RV32-NEXT: addi sp, sp, 16
+; RV32-NEXT: mul a0, a0, a0
; RV32-NEXT: ret
;
; RV64-LABEL: freeze_int:
; RV64: # %bb.0:
-; RV64-NEXT: addi sp, sp, -16
-; RV64-NEXT: .cfi_def_cfa_offset 16
-; RV64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
-; RV64-NEXT: .cfi_offset ra, -8
-; RV64-NEXT: call __muldi3
-; RV64-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
-; RV64-NEXT: addi sp, sp, 16
+; RV64-NEXT: mulw a0, a0, a0
; RV64-NEXT: ret
- %y1 = freeze i32 undef
+ %y1 = freeze i32 %x
%t1 = mul i32 %y1, %y1
ret i32 %t1
}
-define i5 @freeze_int2() {
+define i5 @freeze_int2(i5 %x) {
; RV32-LABEL: freeze_int2:
; RV32: # %bb.0:
-; RV32-NEXT: addi sp, sp, -16
-; RV32-NEXT: .cfi_def_cfa_offset 16
-; RV32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
-; RV32-NEXT: .cfi_offset ra, -4
-; RV32-NEXT: call __mulsi3
-; RV32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
-; RV32-NEXT: addi sp, sp, 16
+; RV32-NEXT: mul a0, a0, a0
; RV32-NEXT: ret
;
; RV64-LABEL: freeze_int2:
; RV64: # %bb.0:
-; RV64-NEXT: addi sp, sp, -16
-; RV64-NEXT: .cfi_def_cfa_offset 16
-; RV64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
-; RV64-NEXT: .cfi_offset ra, -8
-; RV64-NEXT: call __muldi3
-; RV64-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
-; RV64-NEXT: addi sp, sp, 16
+; RV64-NEXT: mulw a0, a0, a0
; RV64-NEXT: ret
- %y1 = freeze i5 undef
+ %y1 = freeze i5 %x
%t1 = mul i5 %y1, %y1
ret i5 %t1
}
-define float @freeze_float() {
+define float @freeze_float(float %x) {
; CHECK-LABEL: freeze_float:
; CHECK: # %bb.0:
-; CHECK-NEXT: fadd.s fa0, fa5, fa5
+; CHECK-NEXT: fadd.s fa0, fa0, fa0
; CHECK-NEXT: ret
- %y1 = freeze float undef
+ %y1 = freeze float %x
%t1 = fadd float %y1, %y1
ret float %t1
}
-; TODO: Support vector return values.
-; define <2 x i32> @freeze_ivec() {
-; %y1 = freeze <2 x i32> undef
+; TODO: Support vector calling conv.
+; define <2 x i32> @freeze_ivec(<2 x i32> %x) {
+; %y1 = freeze <2 x i32> %x
; %t1 = add <2 x i32> %y1, %y1
; ret <2 x i32> %t1
; }
-define ptr @freeze_ptr() {
+define ptr @freeze_ptr(ptr %x) {
; CHECK-LABEL: freeze_ptr:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, a0, 4
; CHECK-NEXT: ret
- %y1 = freeze ptr undef
+ %y1 = freeze ptr %x
%t1 = getelementptr i8, ptr %y1, i64 4
ret ptr %t1
}
-
-define i32 @freeze_struct() {
-; RV32-LABEL: freeze_struct:
-; RV32: # %bb.0:
-; RV32-NEXT: add a0, a0, a0
-; RV32-NEXT: ret
-;
-; RV64-LABEL: freeze_struct:
-; RV64: # %bb.0:
-; RV64-NEXT: addw a0, a0, a0
-; RV64-NEXT: ret
- %y1 = freeze %struct.T undef
- %v1 = extractvalue %struct.T %y1, 0
- %v2 = extractvalue %struct.T %y1, 1
- %t1 = add i32 %v1, %v2
- ret i32 %t1
-}
-
-define i32 @freeze_anonstruct() {
-; RV32-LABEL: freeze_anonstruct:
-; RV32: # %bb.0:
-; RV32-NEXT: add a0, a0, a0
-; RV32-NEXT: ret
-;
-; RV64-LABEL: freeze_anonstruct:
-; RV64: # %bb.0:
-; RV64-NEXT: addw a0, a0, a0
-; RV64-NEXT: ret
- %y1 = freeze {i32, i32} undef
- %v1 = extractvalue {i32, i32} %y1, 0
- %v2 = extractvalue {i32, i32} %y1, 1
- %t1 = add i32 %v1, %v2
- ret i32 %t1
-}
-
-define i32 @freeze_anonstruct2() {
-; RV32-LABEL: freeze_anonstruct2:
-; RV32: # %bb.0:
-; RV32-NEXT: lui a0, 16
-; RV32-NEXT: addi a0, a0, -1
-; RV32-NEXT: and a0, a0, a0
-; RV32-NEXT: add a0, a0, a0
-; RV32-NEXT: ret
-;
-; RV64-LABEL: freeze_anonstruct2:
-; RV64: # %bb.0:
-; RV64-NEXT: lui a0, 16
-; RV64-NEXT: addi a0, a0, -1
-; RV64-NEXT: and a0, a0, a0
-; RV64-NEXT: addw a0, a0, a0
-; RV64-NEXT: ret
- %y1 = freeze {i32, i16} undef
- %v1 = extractvalue {i32, i16} %y1, 0
- %v2 = extractvalue {i32, i16} %y1, 1
- %z2 = zext i16 %v2 to i32
- %t1 = add i32 %v1, %z2
- ret i32 %t1
-}
-
-define i64 @freeze_array() {
-; RV32-LABEL: freeze_array:
-; RV32: # %bb.0:
-; RV32-NEXT: add a0, a0, a0
-; RV32-NEXT: sltu a1, a0, a0
-; RV32-NEXT: add a2, a0, a0
-; RV32-NEXT: add a1, a2, a1
-; RV32-NEXT: ret
-;
-; RV64-LABEL: freeze_array:
-; RV64: # %bb.0:
-; RV64-NEXT: add a0, a0, a0
-; RV64-NEXT: ret
- %y1 = freeze [2 x i64] undef
- %v1 = extractvalue [2 x i64] %y1, 0
- %v2 = extractvalue [2 x i64] %y1, 1
- %t1 = add i64 %v1, %v2
- ret i64 %t1
-}
>From 0f47c04b2a89d9c0087b4cc3c2bedef7ece708dc Mon Sep 17 00:00:00 2001
From: Yingwei Zheng <dtcxzyw2333 at gmail.com>
Date: Tue, 21 May 2024 00:07:17 +0800
Subject: [PATCH 3/4] [GISel][RISCV] Add more tests. NFC.
---
llvm/test/CodeGen/RISCV/GlobalISel/freeze.ll | 57 +++++++++++++++++---
1 file changed, 50 insertions(+), 7 deletions(-)
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/freeze.ll b/llvm/test/CodeGen/RISCV/GlobalISel/freeze.ll
index 5b740b1087d00..f839eafe2af76 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/freeze.ll
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/freeze.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
-; RUN: llc -mtriple=riscv32 -mattr=+f,+m,+v -global-isel -global-isel-abort=1 -verify-machineinstrs < %s 2>&1 | FileCheck %s --check-prefixes=CHECK,RV32
-; RUN: llc -mtriple=riscv64 -mattr=+f,+m,+v -global-isel -global-isel-abort=1 -verify-machineinstrs < %s 2>&1 | FileCheck %s --check-prefixes=CHECK,RV64
+; RUN: llc -mtriple=riscv32 -mattr=+f,+d,+zfh,+m,+v -global-isel -global-isel-abort=1 -verify-machineinstrs < %s 2>&1 | FileCheck %s --check-prefixes=CHECK,RV32
+; RUN: llc -mtriple=riscv64 -mattr=+f,+d,+zfh,+m,+v -global-isel -global-isel-abort=1 -verify-machineinstrs < %s 2>&1 | FileCheck %s --check-prefixes=CHECK,RV64
define i32 @freeze_int(i32 %x) {
; RV32-LABEL: freeze_int:
@@ -42,11 +42,54 @@ define float @freeze_float(float %x) {
ret float %t1
}
-; TODO: Support vector calling conv.
-; define <2 x i32> @freeze_ivec(<2 x i32> %x) {
-; %y1 = freeze <2 x i32> %x
-; %t1 = add <2 x i32> %y1, %y1
-; ret <2 x i32> %t1
+define double @freeze_double(double %x) nounwind {
+; RV32-LABEL: freeze_double:
+; RV32: # %bb.0:
+; RV32-NEXT: addi sp, sp, -16
+; RV32-NEXT: fsd fa0, 8(sp)
+; RV32-NEXT: lw a0, 8(sp)
+; RV32-NEXT: lw a1, 12(sp)
+; RV32-NEXT: sw a0, 8(sp)
+; RV32-NEXT: sw a1, 12(sp)
+; RV32-NEXT: fld fa5, 8(sp)
+; RV32-NEXT: fadd.d fa0, fa5, fa5
+; RV32-NEXT: addi sp, sp, 16
+; RV32-NEXT: ret
+;
+; RV64-LABEL: freeze_double:
+; RV64: # %bb.0:
+; RV64-NEXT: fadd.d fa0, fa0, fa0
+; RV64-NEXT: ret
+ %y1 = freeze double %x
+ %t1 = fadd double %y1, %y1
+ ret double %t1
+}
+
+define void @freeze_half(ptr %p) {
+; CHECK-LABEL: freeze_half:
+; CHECK: # %bb.0:
+; CHECK-NEXT: lh a1, 0(a0)
+; CHECK-NEXT: sh a1, 0(a0)
+; CHECK-NEXT: ret
+ %x = load half, ptr %p
+ %y1 = freeze half %x
+ store half %y1, ptr %p
+ ret void
+}
+
+; FIXME: Legalize G_FREEZE with fixed-length vectors.
+; define void @freeze_ivec(ptr %p) {
+; %x = load <2 x i32>, ptr %p
+; %y = freeze <2 x i32> %x
+; store <2 x i32> %y, ptr %p
+; ret void
+; }
+
+; define void @freeze_fvec(ptr %p) {
+; %x = load <2 x float>, ptr %p
+; %y = freeze <2 x float> %x
+; store <2 x float> %y, ptr %p
+; ret void
; }
define ptr @freeze_ptr(ptr %x) {
>From 5d9703ab440628f9489166a6fc4890823beb38c4 Mon Sep 17 00:00:00 2001
From: Yingwei Zheng <dtcxzyw2333 at gmail.com>
Date: Tue, 21 May 2024 21:07:10 +0800
Subject: [PATCH 4/4] [GISel][RISCV] Add aggregate tests back. NFC.
---
llvm/test/CodeGen/RISCV/GlobalISel/freeze.ll | 97 ++++++++++++++++++++
1 file changed, 97 insertions(+)
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/freeze.ll b/llvm/test/CodeGen/RISCV/GlobalISel/freeze.ll
index f839eafe2af76..90675b2a22cf2 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/freeze.ll
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/freeze.ll
@@ -101,3 +101,100 @@ define ptr @freeze_ptr(ptr %x) {
%t1 = getelementptr i8, ptr %y1, i64 4
ret ptr %t1
}
+
+%struct.T = type { i32, i32 }
+
+define i32 @freeze_struct(ptr %p) {
+; RV32-LABEL: freeze_struct:
+; RV32: # %bb.0:
+; RV32-NEXT: lw a1, 0(a0)
+; RV32-NEXT: lw a0, 4(a0)
+; RV32-NEXT: add a0, a1, a0
+; RV32-NEXT: ret
+;
+; RV64-LABEL: freeze_struct:
+; RV64: # %bb.0:
+; RV64-NEXT: lw a1, 0(a0)
+; RV64-NEXT: lw a0, 4(a0)
+; RV64-NEXT: addw a0, a1, a0
+; RV64-NEXT: ret
+ %s = load %struct.T, ptr %p
+ %y1 = freeze %struct.T %s
+ %v1 = extractvalue %struct.T %y1, 0
+ %v2 = extractvalue %struct.T %y1, 1
+ %t1 = add i32 %v1, %v2
+ ret i32 %t1
+}
+
+define i32 @freeze_anonstruct(ptr %p) {
+; RV32-LABEL: freeze_anonstruct:
+; RV32: # %bb.0:
+; RV32-NEXT: lw a1, 0(a0)
+; RV32-NEXT: lw a0, 4(a0)
+; RV32-NEXT: add a0, a1, a0
+; RV32-NEXT: ret
+;
+; RV64-LABEL: freeze_anonstruct:
+; RV64: # %bb.0:
+; RV64-NEXT: lw a1, 0(a0)
+; RV64-NEXT: lw a0, 4(a0)
+; RV64-NEXT: addw a0, a1, a0
+; RV64-NEXT: ret
+ %s = load {i32, i32}, ptr %p
+ %y1 = freeze {i32, i32} %s
+ %v1 = extractvalue {i32, i32} %y1, 0
+ %v2 = extractvalue {i32, i32} %y1, 1
+ %t1 = add i32 %v1, %v2
+ ret i32 %t1
+}
+
+define i32 @freeze_anonstruct2(ptr %p) {
+; RV32-LABEL: freeze_anonstruct2:
+; RV32: # %bb.0:
+; RV32-NEXT: lh a1, 4(a0)
+; RV32-NEXT: lw a0, 0(a0)
+; RV32-NEXT: lui a2, 16
+; RV32-NEXT: addi a2, a2, -1
+; RV32-NEXT: and a1, a1, a2
+; RV32-NEXT: add a0, a0, a1
+; RV32-NEXT: ret
+;
+; RV64-LABEL: freeze_anonstruct2:
+; RV64: # %bb.0:
+; RV64-NEXT: lh a1, 4(a0)
+; RV64-NEXT: lw a0, 0(a0)
+; RV64-NEXT: lui a2, 16
+; RV64-NEXT: addi a2, a2, -1
+; RV64-NEXT: and a1, a1, a2
+; RV64-NEXT: addw a0, a0, a1
+; RV64-NEXT: ret
+ %s = load {i32, i16}, ptr %p
+ %y1 = freeze {i32, i16} %s
+ %v1 = extractvalue {i32, i16} %y1, 0
+ %v2 = extractvalue {i32, i16} %y1, 1
+ %z2 = zext i16 %v2 to i32
+ %t1 = add i32 %v1, %z2
+ ret i32 %t1
+}
+
+define i32 @freeze_array(ptr %p) nounwind {
+; RV32-LABEL: freeze_array:
+; RV32: # %bb.0:
+; RV32-NEXT: lw a1, 0(a0)
+; RV32-NEXT: lw a0, 4(a0)
+; RV32-NEXT: add a0, a1, a0
+; RV32-NEXT: ret
+;
+; RV64-LABEL: freeze_array:
+; RV64: # %bb.0:
+; RV64-NEXT: lw a1, 0(a0)
+; RV64-NEXT: lw a0, 4(a0)
+; RV64-NEXT: addw a0, a1, a0
+; RV64-NEXT: ret
+ %s = load [2 x i32], ptr %p
+ %y1 = freeze [2 x i32] %s
+ %v1 = extractvalue [2 x i32] %y1, 0
+ %v2 = extractvalue [2 x i32] %y1, 1
+ %t1 = add i32 %v1, %v2
+ ret i32 %t1
+}
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