[llvm] [RISCV] Do not check UsePostRAScheduler in enablePostRAScheduler (PR #92781)

[Pengcheng Wang via llvm-commits]

wangpc-pp wrote:

I think it's messy now as we have two ways to enable PostRAScheduler. For AArch64, which has overrided `enablePostRAScheduler` and only the feature value takes effect, but we can still see some models that set `PostRAScheduler` field in `SchedMachineModel`:
https://github.com/llvm/llvm-project/blob/6658e1a3fdfebfc9d1805029ca0e4de643634927/llvm/lib/Target/AArch64/AArch64SchedA510.td#L17-L29
I think it worths unifying the way for RISCV, and I do prefer to the feature way (I think you have spoken my mind :-)).
We should add a release note, add some comments and so on to emphasize that the setting of `SchedMachineModel`'s `PostRAScheduler` won't do any difference and we should add it to Processor definitions.

https://github.com/llvm/llvm-project/pull/92781