[llvm] [RISCV] Do not check UsePostRAScheduler in enablePostRAScheduler (PR #92781)

[Craig Topper via llvm-commits]

topperc wrote:

Do we need to add FeaturePostRAScheduler to SiFive7, SiFiveP400, and SiFive600 in RISCVProcessors.td?

https://github.com/llvm/llvm-project/pull/92781