[llvm] [AArch64] Lower extending sitofp using tbl (PR #92528)

[David Green via llvm-commits]

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@@ -17840,13 +17887,39 @@ static SDValue performVectorCompareAndMaskUnaryOpCombine(SDNode *N,
   return SDValue();
 }
 
+static SDValue performVectorIntToFpCombine(SDNode *N, SelectionDAG &DAG) {
+  if (N->getOpcode() != ISD::SINT_TO_FP || N->getValueType(0) != MVT::v4f32)
+    return SDValue();
+
+  SDNode *VASHR = N->getOperand(0).getNode();
+  if (VASHR->getOpcode() != AArch64ISD::VASHR ||
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davemgreen wrote:

> Im not sure if this should be matched from shifts in general

I think the shift would need to be exact. https://alive2.llvm.org/ce/z/F9usML. From what I can tell we are trying to add this: https://alive2.llvm.org/ce/z/82h6nn, where the shift would be exact, but that wouldn't be true for other cases.

It would probably be good to get the scvtf_fixed working in one patch first with some testing, and have the tbl loop transform in a second.

https://github.com/llvm/llvm-project/pull/92528