[llvm] [AArch64] Lower extending sitofp using tbl (PR #92528)

[David Green via llvm-commits]

================
@@ -17840,13 +17887,39 @@ static SDValue performVectorCompareAndMaskUnaryOpCombine(SDNode *N,
   return SDValue();
 }
 
+static SDValue performVectorIntToFpCombine(SDNode *N, SelectionDAG &DAG) {
+  if (N->getOpcode() != ISD::SINT_TO_FP || N->getValueType(0) != MVT::v4f32)
+    return SDValue();
+
+  SDNode *VASHR = N->getOperand(0).getNode();
+  if (VASHR->getOpcode() != AArch64ISD::VASHR ||
----------------
davemgreen wrote:

Im not sure if this should be matched from shifts in general. Can we reinstate https://github.com/llvm/llvm-project/pull/91924/files but using fmul and match using that? It would be nice if it could use tablegen like https://reviews.llvm.org/D113199 too, if that is possible.

https://github.com/llvm/llvm-project/pull/92528