[llvm] [RISCV] Move RISCVInsertVSETVLI to after phi elimination (PR #91440)

[Luke Lau via llvm-commits]

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@@ -1176,9 +1176,9 @@ define void @sink_splat_ashr_scalable(ptr nocapture %a) {
 ; CHECK-NEXT:    andi a3, a1, 1024
 ; CHECK-NEXT:    xori a1, a3, 1024
 ; CHECK-NEXT:    slli a4, a4, 1
-; CHECK-NEXT:    vsetvli a5, zero, e32, m2, ta, ma
 ; CHECK-NEXT:    mv a5, a0
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lukel97 wrote:

I gave a very quick stab at moving the vsetvli up before the previous GPR def (so the dead def is immediately reused), and we're able to reuse the GPR and remove the spill in this case. https://github.com/lukel97/llvm-project/commit/fe81aa40df42a53bda6b407888cb2322618f23f5

But on SPEC 2017 it actually seems to increase the number of spills by 0.2%, both on main and when applied to this PR. So it doesn't look like its actually removing any spills that may have been introduced by this PR. 

My guess is that since we have to update LiveIntervals that it's perturbing something in regalloc ever so slightly, or it might actually be moving the vsetvli up into a higher pressure region and backfiring.

This increase in register pressure seems small though (it's limited to just the single instruction slot and it's in the scalar domain, so hopefully less likely to spill than a vector), are we considering it something that needs fixed in this PR? 

https://github.com/llvm/llvm-project/pull/91440