[llvm] [RISCV] Move RISCVInsertVSETVLI to after phi elimination (PR #91440)

[Philip Reames via llvm-commits]

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@@ -1176,9 +1176,9 @@ define void @sink_splat_ashr_scalable(ptr nocapture %a) {
 ; CHECK-NEXT:    andi a3, a1, 1024
 ; CHECK-NEXT:    xori a1, a3, 1024
 ; CHECK-NEXT:    slli a4, a4, 1
-; CHECK-NEXT:    vsetvli a5, zero, e32, m2, ta, ma
 ; CHECK-NEXT:    mv a5, a0
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preames wrote:

To be explicit, I'm fine with this landing without the backwards heuristic as you've removed the diffs by taking them eagerly in another patch, but I would like to see us follow up on this after this series has landed.  I think the scheduling to reduce register pressure is interesting here, and if the scheduler doesn't manage that on it's own after the whole patch sequence, we should look into this more.  

https://github.com/llvm/llvm-project/pull/91440