[llvm] [RISCV] Move RISCVInsertVSETVLI to after phi elimination (PR #91440)

[Piyou Chen via llvm-commits]

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@@ -1155,8 +1155,8 @@ define void @mulhu_v8i16(ptr %x) {
 ; CHECK-NEXT:    vle16.v v8, (a0)
 ; CHECK-NEXT:    vmv.v.i v9, 0
 ; CHECK-NEXT:    lui a1, 1048568
-; CHECK-NEXT:    vsetvli zero, zero, e16, m1, tu, ma
 ; CHECK-NEXT:    vmv.v.i v10, 0
----------------
BeMg wrote:

> Maybe it assume VL/VTYPE dependant doesn't break?
> 
> > NOTE:
> > post-ra pseudo pass invoke `TII->lowerCOPY -> RISCVInstrInfo::copyPhysReg -> RISCVInstrInfo::copyPhysRegVector` to > emit the `PseudoVMV_V_I_M1` base on `COPY`.

No. Machine scheduler could move the COPY before vsetvl. VL/VTYPE dependent doesn't constrain COPY at all. The current scheduled order base on input order. 

```
SU(3):   %6:vr = PseudoVMV_V_I_M1 undef %6:vr(tied-def 0), 0, 8, 4, 0, implicit $vl, implicit $vtype

SU(7) %4:vr = PseudoVMV_S_X %4:vr(tied-def 0), %3:gpr, 8, 4, implicit $vl, implicit $vtype
SU(11) early-clobber %6:vr = PseudoVSLIDEUP_VI_M1 %6:vr(tied-def 0), %5:vr, 6, 7, 4, 0, implicit $vl, implicit $vtype

SU(6):   %4:vr = COPY %6:vr
  Predecessors:
    SU(3): Data Latency=1 Reg=%6
  Successors:
    SU(7): Data Latency=0 Reg=%4
    SU(7): Out  Latency=1
    SU(11): Anti Latency=0
```



https://github.com/llvm/llvm-project/pull/91440