[llvm] ISel/AArch64: custom lower vector ISD::[L]LRINT (PR #89035)
Ramkumar Ramachandra via llvm-commits
llvm-commits at lists.llvm.org
Thu May 9 11:51:35 PDT 2024
================
@@ -4362,6 +4379,25 @@ SDValue AArch64TargetLowering::LowerFP_TO_INT_SAT(SDValue Op,
return DAG.getNode(ISD::TRUNCATE, DL, DstVT, Sat);
}
+SDValue AArch64TargetLowering::LowerVectorXRINT(SDValue Op,
+ SelectionDAG &DAG) const {
+ EVT VT = Op.getValueType();
+ SDValue Src = Op.getOperand(0);
+ SDLoc DL(Op);
+
+ assert(VT.isVector() && "Expected vector type");
+
+ EVT CastVT =
+ VT.changeVectorElementType(Src.getValueType().getVectorElementType());
+
+ // Round the floating-point value into a floating-point register with the
+ // current rounding mode.
+ SDValue FOp = DAG.getNode(ISD::FRINT, DL, CastVT, Src);
+
+ // Truncate the rounded floating point to an integer, rounding to zero.
+ return DAG.getNode(ISD::FP_TO_SINT, DL, VT, FOp);
----------------
artagnon wrote:
I think using FP_TO_SINT_SAT is wrong, as FP_TO_SINT_SAT returns zero on NaN values, while L[L]LRINT raise exceptions on NaN.
https://github.com/llvm/llvm-project/pull/89035
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