[llvm] ISel/AArch64: custom lower vector ISD::[L]LRINT (PR #89035)

[Eli Friedman via llvm-commits]

================
@@ -4362,6 +4379,25 @@ SDValue AArch64TargetLowering::LowerFP_TO_INT_SAT(SDValue Op,
   return DAG.getNode(ISD::TRUNCATE, DL, DstVT, Sat);
 }
 
+SDValue AArch64TargetLowering::LowerVectorXRINT(SDValue Op,
+                                                SelectionDAG &DAG) const {
+  EVT VT = Op.getValueType();
+  SDValue Src = Op.getOperand(0);
+  SDLoc DL(Op);
+
+  assert(VT.isVector() && "Expected vector type");
+
+  EVT CastVT =
+      VT.changeVectorElementType(Src.getValueType().getVectorElementType());
+
+  // Round the floating-point value into a floating-point register with the
+  // current rounding mode.
+  SDValue FOp = DAG.getNode(ISD::FRINT, DL, CastVT, Src);
+
+  // Truncate the rounded floating point to an integer, rounding to zero.
+  return DAG.getNode(ISD::FP_TO_SINT, DL, VT, FOp);
----------------
efriedma-quic wrote:

I think you need to use ISD::FP_TO_SINT_SAT to represent a saturating conversion.  (It shouldn't affect the codegen on AArch64, but if you use the wrong node, other combines might reason about it incorrectly.)

https://github.com/llvm/llvm-project/pull/89035