[llvm] [RISCV] Move RISCVInsertVSETVLI to after phi elimination (PR #91440)

[Philip Reames via llvm-commits]

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@@ -1176,9 +1176,9 @@ define void @sink_splat_ashr_scalable(ptr nocapture %a) {
 ; CHECK-NEXT:    andi a3, a1, 1024
 ; CHECK-NEXT:    xori a1, a3, 1024
 ; CHECK-NEXT:    slli a4, a4, 1
-; CHECK-NEXT:    vsetvli a5, zero, e32, m2, ta, ma
 ; CHECK-NEXT:    mv a5, a0
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preames wrote:

This one is an interesting example.  The destination vreg is presumably dead, and by placing it later in the block we have higher register pressure.  My guess is that these moves come from phi elimination?  If so, maybe we have a slightly different move backwards to reduce register pressure lurking here?

https://github.com/llvm/llvm-project/pull/91440