[llvm] [RISC-V] Limit vscale interleaving to addrspace 0. (PR #91573)

[Harald van Dijk via llvm-commits]

================
@@ -21048,6 +21048,11 @@ bool RISCVTargetLowering::isLegalInterleavedAccessType(
       return false;
 
     ContainerVT = getContainerForFixedLengthVector(VT.getSimpleVT());
+  } else {
----------------
hvdijk wrote:

I was surprised by that too, but seemingly not, see the `load_factor2_as` and `store_factor2_as` tests I added.

https://github.com/llvm/llvm-project/pull/91573