[llvm] [LLVM][AArch64]Use load/store with consecutive registers in SME2 or S… (PR #77665)

[Sander de Smalen via llvm-commits]

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@@ -3287,8 +3351,39 @@ void AArch64FrameLowering::determineCalleeSaves(MachineFunction &MF,
           !RegInfo->isReservedReg(MF, PairedReg))
         ExtraCSSpill = PairedReg;
     }
+
+    // Save PReg in FunctionInfo to build PTRUE instruction later. The PTRUE is
+    // being used in the function to save and restore the pair of ZReg
+    AArch64FunctionInfo *AFI = MF.getInfo<AArch64FunctionInfo>();
+    if (Subtarget.hasSVE2p1() || Subtarget.hasSME2()) {
+      if (AArch64::PPRRegClass.contains(Reg) &&
+          (Reg >= AArch64::P8 && Reg <= AArch64::P15) && SavedRegs.test(Reg) &&
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sdesmalen-arm wrote:

I can't see where you've addressed this. Did you miss this comment?

https://github.com/llvm/llvm-project/pull/77665