[llvm] [LLVM][AArch64]Use load/store with consecutive registers in SME2 or S… (PR #77665)

[Sander de Smalen via llvm-commits]

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@@ -3287,6 +3355,31 @@ void AArch64FrameLowering::determineCalleeSaves(MachineFunction &MF,
           !RegInfo->isReservedReg(MF, PairedReg))
         ExtraCSSpill = PairedReg;
     }
+    // Check if there is a pair of ZRegs, so it can select PReg for spill/fill
+    HasPairZReg |= (AArch64::ZPRRegClass.contains(Reg, CSRegs[i ^ 1]) &&
+                    SavedRegs.test(CSRegs[i ^ 1]));
+  }
+
+  if (HasPairZReg && (Subtarget.hasSVE2p1() || Subtarget.hasSME2())) {
+    AArch64FunctionInfo *AFI = MF.getInfo<AArch64FunctionInfo>();
+    // Find a suitable predicate register for the multi-vector spill/fill
+    // instructions.
+    for (unsigned PReg = AArch64::P8; PReg <= AArch64::P15; ++PReg) {
+      if (SavedRegs.test(PReg)) {
+        AFI->setPredicateRegForFillSpill(PReg - AArch64::P0 + AArch64::PN0);
+        break;
+      }
+    }
+    // If no free callee-save has been found assign one.
+    if (!AFI->getPredicateRegForFillSpill() &&
+        MF.getFunction().getCallingConv() ==
+            CallingConv::AArch64_SVE_VectorCall) {
+      SavedRegs.set(AArch64::P8);
+      AFI->setPredicateRegForFillSpill(AArch64::PN8);
+    }
+
+    assert(!RegInfo->isReservedReg(MF, AFI->getPredicateRegForFillSpill()) &&
----------------
sdesmalen-arm wrote:

nit: Is it worth putting this functionality into a helper function to keep this function a bit simpler?

e.g.
```
if (HasPairZReg && (Subtarget.hasSVE2p1() || Subtarget.hasSME2()))
  if (unsigned Reg = findFreePredicateReg())
    AFI->setPredicateRegForFillSpill(Reg);
```
?

https://github.com/llvm/llvm-project/pull/77665