[llvm] b621269 - [AArch64] Adjust ROBsize for Ampere1B (NFC) (#86331)

[via llvm-commits]

Author: Philipp Tomsich
Date: 2024-03-22T16:30:12-07:00
New Revision: b621269d4a4c08269b1b2d46f277d1918d3dab62

URL: https://github.com/llvm/llvm-project/commit/b621269d4a4c08269b1b2d46f277d1918d3dab62
DIFF: https://github.com/llvm/llvm-project/commit/b621269d4a4c08269b1b2d46f277d1918d3dab62.diff

LOG: [AArch64] Adjust ROBsize for Ampere1B (NFC) (#86331)

To align more closely with common usage, we now use the size of the
reorder-buffer for MicroOpBufferSize instead of the entries of the
global micro-op scheduler.

Added: 
    

Modified: 
    llvm/lib/Target/AArch64/AArch64SchedAmpere1B.td

Removed: 
    


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diff  --git a/llvm/lib/Target/AArch64/AArch64SchedAmpere1B.td b/llvm/lib/Target/AArch64/AArch64SchedAmpere1B.td
index 9c4f000cf351b2..67f8593f1577a3 100644
--- a/llvm/lib/Target/AArch64/AArch64SchedAmpere1B.td
+++ b/llvm/lib/Target/AArch64/AArch64SchedAmpere1B.td
@@ -18,7 +18,7 @@
 
 def Ampere1BModel : SchedMachineModel {
   let IssueWidth            =  12;  // Maximum micro-ops dispatch rate.
-  let MicroOpBufferSize     = 192;  // micro-op re-order buffer size
+  let MicroOpBufferSize     = 208;  // micro-op re-order buffer size
   let LoadLatency           =   3;  // Optimistic load latency
   let MispredictPenalty     =  10;  // Branch mispredict penalty
   let LoopMicroOpBufferSize =  32;  // Instruction queue size