[llvm] af63c6e - [AArch64] Adjust ROBsize for Ampere1/Ampere1A (NFC) (#86330)

[via llvm-commits]

Author: Philipp Tomsich
Date: 2024-03-22T16:29:58-07:00
New Revision: af63c6e5d08fcaeacaeee68aa0a1cda71d9a7549

URL: https://github.com/llvm/llvm-project/commit/af63c6e5d08fcaeacaeee68aa0a1cda71d9a7549
DIFF: https://github.com/llvm/llvm-project/commit/af63c6e5d08fcaeacaeee68aa0a1cda71d9a7549.diff

LOG: [AArch64] Adjust ROBsize for Ampere1/Ampere1A (NFC) (#86330)

To align more closely with common usage, we now use the size of the
reorder-buffer for MicroOpBufferSize instead of the entries of the
global micro-op scheduler.

Added: 
    

Modified: 
    llvm/lib/Target/AArch64/AArch64SchedAmpere1.td

Removed: 
    


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diff  --git a/llvm/lib/Target/AArch64/AArch64SchedAmpere1.td b/llvm/lib/Target/AArch64/AArch64SchedAmpere1.td
index cf9f50c2784bbe..269f4ec5e5fb16 100644
--- a/llvm/lib/Target/AArch64/AArch64SchedAmpere1.td
+++ b/llvm/lib/Target/AArch64/AArch64SchedAmpere1.td
@@ -18,7 +18,7 @@
 
 def Ampere1Model : SchedMachineModel {
   let IssueWidth            =   4;  // 4-way decode and dispatch
-  let MicroOpBufferSize     = 174;  // micro-op re-order buffer size
+  let MicroOpBufferSize     = 192;  // re-order buffer size
   let LoadLatency           =   4;  // Optimistic load latency
   let MispredictPenalty     =  10;  // Branch mispredict penalty
   let LoopMicroOpBufferSize =  32;  // Instruction queue size