[llvm] [ARM][TableGen][MC] Change the ARM mnemonic operands to be optional for ASM parsing (PR #83436)

[Simon Tatham via llvm-commits]

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@@ -6886,19 +6904,17 @@ void ARMAsmParser::fixupGNULDRDAlias(StringRef Mnemonic,
 // operand. If the conversion fails an error is diagnosed, and the function
 // returns true.
 bool ARMAsmParser::CDEConvertDualRegOperand(StringRef Mnemonic,
-                                            OperandVector &Operands) {
+                                            OperandVector &Operands,
+                                            unsigned MnemonicOpsEndInd) {
   assert(MS.isCDEDualRegInstr(Mnemonic));
-  bool isPredicable =
-      Mnemonic == "cx1da" || Mnemonic == "cx2da" || Mnemonic == "cx3da";
-  size_t NumPredOps = isPredicable ? 1 : 0;
 
-  if (Operands.size() <= 3 + NumPredOps)
+  if (Operands.size() < 2 + MnemonicOpsEndInd)
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statham-arm wrote:

Should this be a `<=` instead of `<`? Further down, line 6952, you're dereferencing `Operands[MnemonicOpsEndInd + 2]`, which would be one beyond the end if `Operands.size()` was _exactly_ the value you're comparing it with here.

(The previous code is `<=`, which was what caught my eye)

https://github.com/llvm/llvm-project/pull/83436