[llvm] [ARM][TableGen][MC] Change the ARM mnemonic operands to be optional for ASM parsing (PR #83436)

[Simon Tatham via llvm-commits]

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@@ -7398,71 +7424,83 @@ static bool instIsBreakpoint(const MCInst &Inst) {
            Inst.getOpcode() == ARM::HLT;
 }
 
+unsigned getRegListInd(const OperandVector &Operands,
+                       unsigned MnemonicOpsEndInd) {
+  for (unsigned I = MnemonicOpsEndInd; I < Operands.size(); ++I) {
+    const ARMOperand &Op = static_cast<const ARMOperand &>(*Operands[I]);
+    if (Op.isRegList()) {
+      return I;
+    }
+  }
+  return 0;
+}
+
 bool ARMAsmParser::validatetLDMRegList(const MCInst &Inst,
                                        const OperandVector &Operands,
-                                       unsigned ListNo, bool IsARPop) {
-  const ARMOperand &Op = static_cast<const ARMOperand &>(*Operands[ListNo]);
-  bool HasWritebackToken = Op.isToken() && Op.getToken() == "!";
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statham-arm wrote:

I didn't understand why the new version of this function doesn't need to take account of whether there's a writeback token. In this version, we're checking for one, and using it to adjust the index of the token on which we report an error. The replacement code doens't check.

Line 7994 seems to be checking for a writeback token to set `RegStart`, but it's then not passing the result to this function. So how is the operand index not going to be off by one depending on writeback? Are there tests somewhere demonstrating that this still works?

https://github.com/llvm/llvm-project/pull/83436