[llvm] [ARM][TableGen][MC] Change the ARM mnemonic operands to be optional for ASM parsing (PR #83436)

[Simon Tatham via llvm-commits]

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@@ -1347,6 +1368,14 @@ class ARMOperand : public MCParsedAsmOperand {
   bool isRegListWithAPSR() const {
     return Kind == k_RegisterListWithAPSR || Kind == k_RegisterList;
   }
+  bool isDReg() const {
+    return isReg() &&
+           ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg.RegNum);
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statham-arm wrote:

This looks identical to `isQReg` below – it still checks against `QPRRegClassID`. Shouldn't it have a different id?

https://github.com/llvm/llvm-project/pull/83436