[llvm] [AArch64] SimplifyDemandedBitsForTargetNode - add AArch64ISD::BICi handling (PR #76644)

[David Green via llvm-commits]

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@@ -27526,6 +27539,23 @@ bool AArch64TargetLowering::SimplifyDemandedBitsForTargetNode(
     // used - simplify to just Val.
     return TLO.CombineTo(Op, ShiftR->getOperand(0));
   }
+  case AArch64ISD::BICi: {
+    // Fold BICi if all destination bits already known to be zeroed
+    SDValue Op0 = Op.getOperand(0);
+    KnownBits KnownOp0 =
+        TLO.DAG.computeKnownBits(Op0, OriginalDemandedElts, Depth + 1);
+    // Op0 &= ~(ConstantOperandVal(1) << ConstantOperandVal(2))
+    uint64_t BitsToClear = Op->getConstantOperandVal(1)
+                           << Op->getConstantOperandVal(2);
+    APInt AlreadyZeroedBitsToClear = BitsToClear & KnownOp0.Zero;
+    if (APInt(Known.getBitWidth(), BitsToClear)
+            .isSubsetOf(AlreadyZeroedBitsToClear))
+      return TLO.CombineTo(Op, Op0);
+
+    Known &= KnownBits::makeConstant(APInt(Known.getBitWidth(), ~BitsToClear));
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davemgreen wrote:

Could this be `Known = KnownOp0 & KnownBits::makeConstant(APInt(Known.getBitWidth(), ~BitsToClear));`? There is already some code for this in AArch64TargetLowering::computeKnownBitsForTargetNode, I would guess these should match in terms of what they produce, but sometimes I mis-understand exactly what SimplifyDemandedBitsForTargetNode should be doing. I think this could be quite similar to the ISD::AND case inside SimplifyDemandedBits, just with an always-constant second argument.

https://github.com/llvm/llvm-project/pull/76644