[llvm] [AArch64] SimplifyDemandedBitsForTargetNode - add AArch64ISD::BICi handling (PR #76644)

[Jay Foad via llvm-commits]

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@@ -3416,13 +3416,18 @@ KnownBits SelectionDAG::computeKnownBits(SDValue Op, const APInt &DemandedElts,
       Known = KnownBits::mulhs(Known, Known2);
     break;
   }
-  case ISD::AVGCEILU: {
+  case ISD::AVGFLOORU:
+  case ISD::AVGCEILU:
+  case ISD::AVGFLOORS:
+  case ISD::AVGCEILS: {
+    bool IsCeil = Opcode == ISD::AVGCEILU || Opcode == ISD::AVGCEILS;
+    bool IsSigned = Opcode == ISD::AVGFLOORS || Opcode == ISD::AVGCEILS;
     Known = computeKnownBits(Op.getOperand(0), DemandedElts, Depth + 1);
     Known2 = computeKnownBits(Op.getOperand(1), DemandedElts, Depth + 1);
-    Known = Known.zext(BitWidth + 1);
+    Known = IsSigned ? Known.sext(BitWidth + 1) : Known.zext(BitWidth + 1);
     Known2 = Known2.zext(BitWidth + 1);
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jayfoad wrote:

> BTW, shouldn't we sext/zext(BitWidth + 2) for Ceil versions?

It's not necessary even though the Ceil versions add 1 for carry. E.g. with 8 bits the maximum you could get would be 0xFF + 0xFF + 1 which is 0x1FF which still fits in 9 bits - you don't need 10 bits.

https://github.com/llvm/llvm-project/pull/76644