[llvm] [X86] Transform `(xor x, SIGN_BIT)` -> `(add x, SIGN_BIT)` 32 bit and smaller scalars (PR #83659)

[via llvm-commits]

goldsteinn wrote:

> > We already do some of this in X86DAGToDAGISel::matchAddressRecursively - maybe see why these cases weren't working there?
> 
> I see:
> 
> ```
>   case ISD::OR:
>   case ISD::XOR:
>     // See if we can treat the OR/XOR node as an ADD node.
>     if (!CurDAG->isADDLike(N))
>       break;
>     [[fallthrough]];
>   case ISD::ADD:
>     if (!matchAdd(N, AM, Depth))
>       return false;
>     break;
> ```
> 
> Which isn't quite the same, or is there another transform im missing?
> 
> But it looks to me like whatever we are doing in `DAGToDag` isn't handling non-i32 types.

I tested a patch that transforms `IsAddLike` to `add` in `DAGToDAG` and it has a lot of changes. Im going to replace this impl with that.

https://github.com/llvm/llvm-project/pull/83659