[llvm] [TTI][RISCV]Improve costs for whole vector reg extract/insert. (PR #80164)

[Luke Lau via llvm-commits]

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@@ -432,12 +444,19 @@ InstructionCost RISCVTTIImpl::getShuffleCost(TTI::ShuffleKind Kind,
     // must be implemented here.
     break;
   case TTI::SK_ExtractSubvector:
+    // Extract at zero is always a subregister extract
+    if (Index == 0)
+      return TTI::TCC_Free;
+
     // Example sequence:
     // vsetivli     zero, 4, e8, mf2, tu, ma (ignored)
     // vslidedown.vi  v8, v9, 2
     return LT.first *
            getRISCVInstructionCost(RISCV::VSLIDEDOWN_VI, LT.second, CostKind);
   case TTI::SK_InsertSubvector:
+    if (Index == 0 && any_of(Args, UndefValue::classof))
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lukel97 wrote:

Now that you mention it in https://github.com/llvm/llvm-project/pull/81818#discussion_r1492834518, the args here aren't necessarily the vector and subvector right? I think they're the arguments to the shufflevector instruction.

So maybe there isn't an easy way to handle the scalable insert case after all. 

https://github.com/llvm/llvm-project/pull/80164