[llvm] [TTI][RISCV]Improve costs for whole vector reg extract/insert. (PR #80164)

[Luke Lau via llvm-commits]

================
@@ -326,6 +326,18 @@ InstructionCost RISCVTTIImpl::getShuffleCost(TTI::ShuffleKind Kind,
     switch (Kind) {
     default:
       break;
+    case TTI::SK_InsertSubvector:
+      if (auto *FSubTy = dyn_cast<FixedVectorType>(SubTp)) {
+        unsigned TpRegs = getRegUsageForType(Tp);
+        unsigned SubTpRegs = getRegUsageForType(SubTp);
+        unsigned NextSubTpRegs = getRegUsageForType(FixedVectorType::get(
+            Tp->getElementType(), FSubTy->getNumElements() + 1));
+        // Whole vector insert - just the vector itself.
+        if (Index == 0 && SubTpRegs != 0 && SubTpRegs != NextSubTpRegs &&
----------------
lukel97 wrote:

Just want to check, is `SubTpRegs != NextSubTpRegs` to check that SubTp isn't a fractional LMUL?

https://github.com/llvm/llvm-project/pull/80164