[llvm] [CodeGen] Simplify updateLiveIn in MachineSink (PR #79831)

[Jay Foad via llvm-commits]

jayfoad wrote:

> > This simplifies the code and matches other places where a whole register is marked as livein.
> 
> What you are saying is other places don't bother getting this extra detail.

Yes. `LaneBitmask::getAll` is used as a default in a lot of places, so I assume that it should always be treated identically to the more accurate mask that we used to calculate here.

> What does this impact? For instance, does this makes the verifier less accurate, etc.?

I don't know for sure. I just know that it does not have much effect on the existing lit tests.

> > This also avoids problems when regunits that are synthesized by TableGen
> > to represent ad hoc aliasing have a lane mask of 0.
> 
> I have mixed feeling about that. On one hand, I feel we are working around a real problem. On the other hand, I feel that using aliases in this way (ad hoc) is an abuse of the system.

You mean the whole tablegen `Register` field `list<Register> Aliases = [];` mechanism is an abuse of the system? Maybe, but it seems like quite a lot of work to get rid of the existing in-tree uses.

By the way I have yet another idea for fixing the reported problem. Currently if a leaf register has an ad hoc alias, tablegen will give it a regunit to represent the alias but it will not give it its own "leaf" regunit. My idea is that we could change that, so that leaf registers always get a unique leaf regunit, in addition to any regunits for ad hoc aliasing. This is something that I need anyway for another project: converting MRI / TRI to track reserved regunits instead of reserved registers.

https://github.com/llvm/llvm-project/pull/79831