[llvm] [CodeGen] Simplify updateLiveIn in MachineSink (PR #79831)

[Quentin Colombet via llvm-commits]

qcolombet wrote:

> This simplifies the code and matches other places where a whole register is marked as livein.

What you are saying is other places don't bother getting this extra detail.

What does this impact?
For instance, does this makes the verifier less accurate, etc.?

> This also avoids problems when regunits that are synthesized by TableGen
to represent ad hoc aliasing have a lane mask of 0.

I have mixed feeling about that.
On one hand, I feel we are working around a real problem. On the other hand, I feel that using aliases in this way (ad hoc) is an abuse of the system.

https://github.com/llvm/llvm-project/pull/79831