[llvm] [MVE] Expand64BitShift - handle all constant shift amounts less than 32 (RFC) (PR #81261)

Simon Pilgrim via llvm-commits llvm-commits at lists.llvm.org
Fri Feb 9 08:17:28 PST 2024


RKSimon wrote:

I can't find a definitive explanation of the ARMISD::LSLL/LSRL instructions - how similar to ISD::FSHL/FSHR funnel shifts are they and could we try to lower via them instead to make use of their existing combines?

https://github.com/llvm/llvm-project/pull/81261


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