[llvm] [MVE] Expand64BitShift - handle all constant shift amounts less than 32 (RFC) (PR #81261)

[David Green via llvm-commits]

https://github.com/davemgreen approved this pull request.

> I can't find a definitive explanation of the ARMISD::LSLL/LSRL instructions - how similar to ISD::FSHL/FSHR funnel shifts are they and could we try to lower via them instead to make use of their existing combines?

I think they can have negative and oversized shift amounts. That can't happen for constants but could happen for the register variants. It would be nice to use target independent nodes where we can.

Considering what this changes I think it looks OK to me. Were you running into other cases where it was getting worse too?

https://github.com/llvm/llvm-project/pull/81261