[llvm] [MVE] Expand64BitShift - handle all constant shift amounts less than 32 (RFC) (PR #81261)
via llvm-commits
llvm-commits at lists.llvm.org
Fri Feb 9 08:06:01 PST 2024
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-arm
Author: Simon Pilgrim (RKSimon)
<details>
<summary>Changes</summary>
Expand64BitShift was always dropping to generic shift legalization if the shift amount type was larger than i64, even if the constant shift amount was actually very small. I've adjusted the constant bounds checks to work with APInt types so we can always perform the comparison.
This results in the MVE long shift instructions being used more often, and it looks like this is preventing some additional combines from happening - I'd appreciate any suggestions on what needs to be done - should the Expand64BitShift logic be different and fallback to generic shift legalization more often?
This came about while I was trying to extend the DAGTypeLegalizer::ExpandShift* helpers and need to move to consistently using the legal shift amount types instead of reusing the shift amount type from the original wider shift.
---
Patch is 149.47 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/81261.diff
3 Files Affected:
- (modified) llvm/lib/Target/ARM/ARMISelLowering.cpp (+2-2)
- (modified) llvm/test/CodeGen/Thumb2/mve-fptosi-sat-vector.ll (+861-842)
- (modified) llvm/test/CodeGen/Thumb2/mve-fptoui-sat-vector.ll (+682-645)
``````````diff
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp
index b5c4a8a322ea7f..b98006ed0cb3f4 100644
--- a/llvm/lib/Target/ARM/ARMISelLowering.cpp
+++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp
@@ -6702,8 +6702,8 @@ static SDValue Expand64BitShift(SDNode *N, SelectionDAG &DAG,
// If the shift amount is greater than 32 or has a greater bitwidth than 64
// then do the default optimisation
- if (ShAmt->getValueType(0).getSizeInBits() > 64 ||
- (Con && (Con->getZExtValue() == 0 || Con->getZExtValue() >= 32)))
+ if ((!Con && ShAmt->getValueType(0).getSizeInBits() > 64) ||
+ (Con && (Con->getAPIntValue() == 0 || Con->getAPIntValue().uge(32))))
return SDValue();
// Extract the lower 32 bits of the shift amount if it's not an i32
diff --git a/llvm/test/CodeGen/Thumb2/mve-fptosi-sat-vector.ll b/llvm/test/CodeGen/Thumb2/mve-fptosi-sat-vector.ll
index 3ca01cfa3a8f77..570834fb670100 100644
--- a/llvm/test/CodeGen/Thumb2/mve-fptosi-sat-vector.ll
+++ b/llvm/test/CodeGen/Thumb2/mve-fptosi-sat-vector.ll
@@ -1821,44 +1821,42 @@ define arm_aapcs_vfpcc <4 x i32> @test_signed_v4f32_v4i32_duplicate(<4 x float>
define arm_aapcs_vfpcc <4 x i50> @test_signed_v4f32_v4i50(<4 x float> %f) {
; CHECK-LABEL: test_signed_v4f32_v4i50:
; CHECK: @ %bb.0:
-; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, lr}
-; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, r9, lr}
-; CHECK-NEXT: .pad #4
-; CHECK-NEXT: sub sp, #4
+; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, lr}
+; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, r9, r10, lr}
; CHECK-NEXT: .vsave {d8, d9, d10, d11}
; CHECK-NEXT: vpush {d8, d9, d10, d11}
; CHECK-NEXT: vmov q4, q0
; CHECK-NEXT: mov r8, r0
-; CHECK-NEXT: vmov r0, s17
+; CHECK-NEXT: vmov r0, s18
; CHECK-NEXT: bl __aeabi_f2lz
; CHECK-NEXT: mov r9, r0
; CHECK-NEXT: vmov r0, s19
; CHECK-NEXT: vldr s20, .LCPI28_0
-; CHECK-NEXT: mov r7, r1
-; CHECK-NEXT: vmov r4, s16
-; CHECK-NEXT: vcmp.f32 s17, s20
+; CHECK-NEXT: mov r5, r1
+; CHECK-NEXT: vmov r6, s16
+; CHECK-NEXT: vcmp.f32 s18, s20
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: itt lt
-; CHECK-NEXT: movlt r7, #0
-; CHECK-NEXT: movtlt r7, #65534
+; CHECK-NEXT: movlt r5, #0
+; CHECK-NEXT: movtlt r5, #65534
; CHECK-NEXT: bl __aeabi_f2lz
; CHECK-NEXT: vldr s22, .LCPI28_1
; CHECK-NEXT: vcmp.f32 s19, s20
-; CHECK-NEXT: mov r6, r0
+; CHECK-NEXT: mov r4, r0
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: mov r5, r1
-; CHECK-NEXT: mov r0, r4
-; CHECK-NEXT: vcmp.f32 s17, s22
+; CHECK-NEXT: mov r7, r1
+; CHECK-NEXT: mov r0, r6
+; CHECK-NEXT: vcmp.f32 s18, s22
; CHECK-NEXT: itt lt
-; CHECK-NEXT: movlt r5, #0
-; CHECK-NEXT: movtlt r5, #65534
+; CHECK-NEXT: movlt r7, #0
+; CHECK-NEXT: movtlt r7, #65534
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: itt gt
-; CHECK-NEXT: movwgt r7, #65535
-; CHECK-NEXT: movtgt r7, #1
+; CHECK-NEXT: movwgt r5, #65535
+; CHECK-NEXT: movtgt r5, #1
; CHECK-NEXT: bl __aeabi_f2lz
; CHECK-NEXT: vcmp.f32 s16, s20
-; CHECK-NEXT: mov r4, r1
+; CHECK-NEXT: mov r10, r1
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vcmp.f32 s19, s22
; CHECK-NEXT: it lt
@@ -1866,109 +1864,103 @@ define arm_aapcs_vfpcc <4 x i50> @test_signed_v4f32_v4i50(<4 x float> %f) {
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vcmp.f32 s16, s22
; CHECK-NEXT: itt gt
-; CHECK-NEXT: movwgt r5, #65535
-; CHECK-NEXT: movtgt r5, #1
+; CHECK-NEXT: movwgt r7, #65535
+; CHECK-NEXT: movtgt r7, #1
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s16, s16
; CHECK-NEXT: it gt
; CHECK-NEXT: movgt.w r0, #-1
+; CHECK-NEXT: vcmp.f32 s16, s16
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s19, s20
; CHECK-NEXT: it vs
; CHECK-NEXT: movvs r0, #0
+; CHECK-NEXT: str.w r0, [r8]
+; CHECK-NEXT: vmov r0, s17
+; CHECK-NEXT: vcmp.f32 s19, s20
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vcmp.f32 s19, s22
-; CHECK-NEXT: str.w r0, [r8]
; CHECK-NEXT: it lt
-; CHECK-NEXT: movlt r6, #0
+; CHECK-NEXT: movlt r4, #0
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vcmp.f32 s19, s19
; CHECK-NEXT: it gt
-; CHECK-NEXT: movgt.w r6, #-1
+; CHECK-NEXT: movgt.w r4, #-1
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s17, s17
+; CHECK-NEXT: vcmp.f32 s18, s20
; CHECK-NEXT: itt vs
-; CHECK-NEXT: movvs r6, #0
-; CHECK-NEXT: movvs r5, #0
-; CHECK-NEXT: lsls r0, r5, #22
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s17, s20
-; CHECK-NEXT: orr.w r0, r0, r6, lsr #10
-; CHECK-NEXT: str.w r0, [r8, #20]
-; CHECK-NEXT: it vs
+; CHECK-NEXT: movvs r4, #0
; CHECK-NEXT: movvs r7, #0
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: it lt
; CHECK-NEXT: movlt.w r9, #0
-; CHECK-NEXT: vcmp.f32 s17, s22
+; CHECK-NEXT: vcmp.f32 s18, s22
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: it gt
; CHECK-NEXT: movgt.w r9, #-1
-; CHECK-NEXT: vcmp.f32 s17, s17
+; CHECK-NEXT: vcmp.f32 s18, s18
+; CHECK-NEXT: mov r1, r7
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: it vs
+; CHECK-NEXT: itt vs
; CHECK-NEXT: movvs.w r9, #0
-; CHECK-NEXT: lsr.w r0, r9, #14
-; CHECK-NEXT: orr.w r1, r0, r7, lsl #18
-; CHECK-NEXT: vmov r0, s18
-; CHECK-NEXT: str.w r1, [r8, #8]
+; CHECK-NEXT: movvs r5, #0
+; CHECK-NEXT: bfc r1, #18, #14
+; CHECK-NEXT: vcmp.f32 s16, s20
+; CHECK-NEXT: bfc r5, #18, #14
+; CHECK-NEXT: mov r6, r9
+; CHECK-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-NEXT: lsll r4, r1, #22
+; CHECK-NEXT: lsrl r6, r5, #28
+; CHECK-NEXT: itt lt
+; CHECK-NEXT: movwlt r10, #0
+; CHECK-NEXT: movtlt r10, #65534
+; CHECK-NEXT: vcmp.f32 s16, s22
+; CHECK-NEXT: orrs r1, r5
+; CHECK-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-NEXT: itt gt
+; CHECK-NEXT: movwgt r10, #65535
+; CHECK-NEXT: movtgt r10, #1
+; CHECK-NEXT: str.w r1, [r8, #20]
; CHECK-NEXT: bl __aeabi_f2lz
-; CHECK-NEXT: vcmp.f32 s18, s20
-; CHECK-NEXT: lsrs r2, r5, #10
+; CHECK-NEXT: vcmp.f32 s17, s20
+; CHECK-NEXT: orr.w r2, r6, r4
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s18, s22
; CHECK-NEXT: itt lt
; CHECK-NEXT: movlt r1, #0
; CHECK-NEXT: movtlt r1, #65534
+; CHECK-NEXT: vcmp.f32 s17, s22
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s16, s20
; CHECK-NEXT: itt gt
; CHECK-NEXT: movwgt r1, #65535
; CHECK-NEXT: movtgt r1, #1
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s16, s22
-; CHECK-NEXT: itt lt
-; CHECK-NEXT: movlt r4, #0
-; CHECK-NEXT: movtlt r4, #65534
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s18, s20
-; CHECK-NEXT: itt gt
-; CHECK-NEXT: movwgt r4, #65535
-; CHECK-NEXT: movtgt r4, #1
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s18, s22
+; CHECK-NEXT: str.w r2, [r8, #16]
+; CHECK-NEXT: lsrs r2, r7, #10
+; CHECK-NEXT: vcmp.f32 s17, s20
; CHECK-NEXT: strb.w r2, [r8, #24]
+; CHECK-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: it lt
; CHECK-NEXT: movlt r0, #0
+; CHECK-NEXT: vcmp.f32 s17, s22
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s18, s18
; CHECK-NEXT: it gt
; CHECK-NEXT: movgt.w r0, #-1
+; CHECK-NEXT: vcmp.f32 s17, s17
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: ubfx r2, r7, #14, #4
-; CHECK-NEXT: vcmp.f32 s16, s16
-; CHECK-NEXT: it vs
+; CHECK-NEXT: itt vs
; CHECK-NEXT: movvs r0, #0
-; CHECK-NEXT: orr.w r2, r2, r0, lsl #4
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: str.w r2, [r8, #12]
-; CHECK-NEXT: it vs
-; CHECK-NEXT: movvs r4, #0
-; CHECK-NEXT: vcmp.f32 s18, s18
-; CHECK-NEXT: bfc r4, #18, #14
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: orr.w r2, r4, r9, lsl #18
-; CHECK-NEXT: str.w r2, [r8, #4]
-; CHECK-NEXT: it vs
; CHECK-NEXT: movvs r1, #0
-; CHECK-NEXT: lsrs r0, r0, #28
; CHECK-NEXT: bfc r1, #18, #14
-; CHECK-NEXT: orr.w r0, r0, r1, lsl #4
-; CHECK-NEXT: orr.w r0, r0, r6, lsl #22
-; CHECK-NEXT: str.w r0, [r8, #16]
+; CHECK-NEXT: mov r2, r0
+; CHECK-NEXT: lsrl r2, r1, #14
+; CHECK-NEXT: vcmp.f32 s16, s16
+; CHECK-NEXT: orr.w r1, r1, r9, lsl #4
+; CHECK-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-NEXT: strd r2, r1, [r8, #8]
+; CHECK-NEXT: it vs
+; CHECK-NEXT: movvs.w r10, #0
+; CHECK-NEXT: bfc r10, #18, #14
+; CHECK-NEXT: orr.w r0, r10, r0, lsl #18
+; CHECK-NEXT: str.w r0, [r8, #4]
; CHECK-NEXT: vpop {d8, d9, d10, d11}
-; CHECK-NEXT: add sp, #4
-; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, r9, pc}
+; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, pc}
; CHECK-NEXT: .p2align 2
; CHECK-NEXT: @ %bb.1:
; CHECK-NEXT: .LCPI28_0:
@@ -2120,21 +2112,22 @@ define arm_aapcs_vfpcc <4 x i64> @test_signed_v4f32_v4i64(<4 x float> %f) {
define arm_aapcs_vfpcc <4 x i100> @test_signed_v4f32_v4i100(<4 x float> %f) {
; CHECK-LABEL: test_signed_v4f32_v4i100:
; CHECK: @ %bb.0:
-; CHECK-NEXT: .save {r4, r5, r6, r7, lr}
-; CHECK-NEXT: push {r4, r5, r6, r7, lr}
+; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, r11, lr}
+; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, r9, r10, r11, lr}
; CHECK-NEXT: .pad #4
; CHECK-NEXT: sub sp, #4
; CHECK-NEXT: .vsave {d8, d9, d10, d11}
; CHECK-NEXT: vpush {d8, d9, d10, d11}
; CHECK-NEXT: vmov q4, q0
-; CHECK-NEXT: mov r4, r0
+; CHECK-NEXT: mov r9, r0
; CHECK-NEXT: vmov r0, s18
-; CHECK-NEXT: vldr s20, .LCPI30_0
-; CHECK-NEXT: vmov r7, s19
-; CHECK-NEXT: vmov r5, s16
; CHECK-NEXT: bl __fixsfti
-; CHECK-NEXT: vldr s22, .LCPI30_1
-; CHECK-NEXT: mov r6, r3
+; CHECK-NEXT: mov r10, r3
+; CHECK-NEXT: vmov r3, s16
+; CHECK-NEXT: vldr s22, .LCPI30_0
+; CHECK-NEXT: vmov r7, s17
+; CHECK-NEXT: vldr s20, .LCPI30_1
+; CHECK-NEXT: vmov r4, s19
; CHECK-NEXT: vcmp.f32 s18, s22
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vcmp.f32 s18, s20
@@ -2150,7 +2143,7 @@ define arm_aapcs_vfpcc <4 x i100> @test_signed_v4f32_v4i100(<4 x float> %f) {
; CHECK-NEXT: movvs r2, #0
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vcmp.f32 s18, s20
-; CHECK-NEXT: str.w r2, [r4, #33]
+; CHECK-NEXT: str.w r2, [r9, #33]
; CHECK-NEXT: it lt
; CHECK-NEXT: movlt r1, #0
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
@@ -2162,7 +2155,7 @@ define arm_aapcs_vfpcc <4 x i100> @test_signed_v4f32_v4i100(<4 x float> %f) {
; CHECK-NEXT: it vs
; CHECK-NEXT: movvs r1, #0
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: str.w r1, [r4, #29]
+; CHECK-NEXT: str.w r1, [r9, #29]
; CHECK-NEXT: it lt
; CHECK-NEXT: movlt r0, #0
; CHECK-NEXT: vcmp.f32 s18, s20
@@ -2173,11 +2166,11 @@ define arm_aapcs_vfpcc <4 x i100> @test_signed_v4f32_v4i100(<4 x float> %f) {
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: it vs
; CHECK-NEXT: movvs r0, #0
-; CHECK-NEXT: str.w r0, [r4, #25]
-; CHECK-NEXT: mov r0, r5
+; CHECK-NEXT: str.w r0, [r9, #25]
+; CHECK-NEXT: mov r0, r3
; CHECK-NEXT: bl __fixsfti
; CHECK-NEXT: vcmp.f32 s16, s22
-; CHECK-NEXT: mov r5, r3
+; CHECK-NEXT: mov r11, r3
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vcmp.f32 s16, s20
; CHECK-NEXT: it lt
@@ -2192,7 +2185,7 @@ define arm_aapcs_vfpcc <4 x i100> @test_signed_v4f32_v4i100(<4 x float> %f) {
; CHECK-NEXT: movvs r2, #0
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vcmp.f32 s16, s20
-; CHECK-NEXT: str r2, [r4, #8]
+; CHECK-NEXT: str.w r2, [r9, #8]
; CHECK-NEXT: it lt
; CHECK-NEXT: movlt r1, #0
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
@@ -2204,7 +2197,7 @@ define arm_aapcs_vfpcc <4 x i100> @test_signed_v4f32_v4i100(<4 x float> %f) {
; CHECK-NEXT: it vs
; CHECK-NEXT: movvs r1, #0
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: str r1, [r4, #4]
+; CHECK-NEXT: str.w r1, [r9, #4]
; CHECK-NEXT: it lt
; CHECK-NEXT: movlt r0, #0
; CHECK-NEXT: vcmp.f32 s16, s20
@@ -2215,165 +2208,165 @@ define arm_aapcs_vfpcc <4 x i100> @test_signed_v4f32_v4i100(<4 x float> %f) {
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: it vs
; CHECK-NEXT: movvs r0, #0
-; CHECK-NEXT: str r0, [r4]
-; CHECK-NEXT: mov r0, r7
+; CHECK-NEXT: str.w r0, [r9]
+; CHECK-NEXT: mov r0, r4
; CHECK-NEXT: bl __fixsfti
; CHECK-NEXT: vcmp.f32 s19, s22
+; CHECK-NEXT: mov r6, r0
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vcmp.f32 s19, s20
; CHECK-NEXT: it lt
-; CHECK-NEXT: movlt r1, #0
+; CHECK-NEXT: movlt r6, #0
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vcmp.f32 s19, s19
; CHECK-NEXT: it gt
-; CHECK-NEXT: movgt.w r1, #-1
+; CHECK-NEXT: movgt.w r6, #-1
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s19, s22
+; CHECK-NEXT: vcmp.f32 s18, s22
; CHECK-NEXT: it vs
-; CHECK-NEXT: movvs r1, #0
+; CHECK-NEXT: movvs r6, #0
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s19, s20
; CHECK-NEXT: it lt
-; CHECK-NEXT: movlt r2, #0
+; CHECK-NEXT: mvnlt r10, #7
+; CHECK-NEXT: vcmp.f32 s18, s20
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s19, s19
; CHECK-NEXT: it gt
-; CHECK-NEXT: movgt.w r2, #-1
+; CHECK-NEXT: movgt.w r10, #7
+; CHECK-NEXT: vcmp.f32 s18, s18
+; CHECK-NEXT: mov r5, r1
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: lsr.w r7, r1, #28
-; CHECK-NEXT: vcmp.f32 s19, s22
; CHECK-NEXT: it vs
-; CHECK-NEXT: movvs r2, #0
-; CHECK-NEXT: orr.w r7, r7, r2, lsl #4
+; CHECK-NEXT: movvs.w r10, #0
+; CHECK-NEXT: and r0, r10, #15
+; CHECK-NEXT: mov r4, r2
+; CHECK-NEXT: orr.w r0, r0, r6, lsl #4
+; CHECK-NEXT: str.w r0, [r9, #37]
+; CHECK-NEXT: mov r0, r7
+; CHECK-NEXT: mov r8, r3
+; CHECK-NEXT: bl __fixsfti
+; CHECK-NEXT: vcmp.f32 s17, s22
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: str.w r7, [r4, #45]
+; CHECK-NEXT: vcmp.f32 s17, s20
; CHECK-NEXT: it lt
; CHECK-NEXT: movlt r0, #0
-; CHECK-NEXT: vcmp.f32 s19, s20
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-NEXT: vcmp.f32 s17, s17
; CHECK-NEXT: it gt
; CHECK-NEXT: movgt.w r0, #-1
-; CHECK-NEXT: vcmp.f32 s19, s19
-; CHECK-NEXT: lsrs r2, r2, #28
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-NEXT: vcmp.f32 s16, s22
; CHECK-NEXT: it vs
; CHECK-NEXT: movvs r0, #0
-; CHECK-NEXT: lsrs r7, r0, #28
-; CHECK-NEXT: vcmp.f32 s19, s22
-; CHECK-NEXT: orr.w r7, r7, r1, lsl #4
-; CHECK-NEXT: vmov r1, s17
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s19, s20
-; CHECK-NEXT: str.w r7, [r4, #41]
+; CHECK-NEXT: vcmp.f32 s16, s20
; CHECK-NEXT: it lt
-; CHECK-NEXT: mvnlt r3, #7
+; CHECK-NEXT: mvnlt r11, #7
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s19, s19
+; CHECK-NEXT: vcmp.f32 s16, s16
; CHECK-NEXT: it gt
-; CHECK-NEXT: movgt r3, #7
+; CHECK-NEXT: movgt.w r11, #7
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s18, s22
+; CHECK-NEXT: vcmp.f32 s19, s22
; CHECK-NEXT: it vs
-; CHECK-NEXT: movvs r3, #0
-; CHECK-NEXT: orr.w r2, r2, r3, lsl #4
+; CHECK-NEXT: movvs.w r11, #0
+; CHECK-NEXT: and r7, r11, #15
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: strb.w r2, [r4, #49]
+; CHECK-NEXT: vcmp.f32 s19, s20
+; CHECK-NEXT: orr.w r7, r7, r0, lsl #4
+; CHECK-NEXT: str.w r7, [r9, #12]
; CHECK-NEXT: it lt
-; CHECK-NEXT: mvnlt r6, #7
-; CHECK-NEXT: vcmp.f32 s18, s20
+; CHECK-NEXT: movlt r5, #0
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-NEXT: vcmp.f32 s19, s19
; CHECK-NEXT: it gt
-; CHECK-NEXT: movgt r6, #7
-; CHECK-NEXT: vcmp.f32 s18, s18
+; CHECK-NEXT: movgt.w r5, #-1
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-NEXT: vcmp.f32 s19, s22
; CHECK-NEXT: it vs
-; CHECK-NEXT: movvs r6, #0
-; CHECK-NEXT: and r2, r6, #15
-; CHECK-NEXT: orr.w r0, r2, r0, lsl #4
-; CHECK-NEXT: str.w r0, [r4, #37]
-; CHECK-NEXT: mov r0, r1
-; CHECK-NEXT: bl __fixsfti
-; CHECK-NEXT: vcmp.f32 s17, s22
+; CHECK-NEXT: movvs r5, #0
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s17, s20
+; CHECK-NEXT: vcmp.f32 s19, s20
; CHECK-NEXT: it lt
-; CHECK-NEXT: movlt r1, #0
+; CHECK-NEXT: movlt r4, #0
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s17, s17
+; CHECK-NEXT: vcmp.f32 s19, s19
; CHECK-NEXT: it gt
-; CHECK-NEXT: movgt.w r1, #-1
+; CHECK-NEXT: movgt.w r4, #-1
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s17, s22
+; CHECK-NEXT: lsrl r6, r5, #28
+; CHECK-NEXT: vcmp.f32 s19, s22
; CHECK-NEXT: it vs
-; CHECK-NEXT: movvs r1, #0
+; CHECK-NEXT: movvs r4, #0
+; CHECK-NEXT: orr.w r7, r5, r4, lsl #4
+; CHECK-NEXT: str.w r7, [r9, #45]
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s17, s20
+; CHECK-NEXT: str.w r6, [r9, #41]
; CHECK-NEXT: it lt
-; CHECK-NEXT: movlt r2, #0
+; CHECK-NEXT: mvnlt r8, #7
+; CHECK-NEXT: vcmp.f32 s19, s20
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s17, s17
; CHECK-NEXT: it gt
-; CHECK-NEXT: movgt.w r2, #-1
+; CHECK-NEXT: movgt.w r8, #7
+; CHECK-NEXT: vcmp.f32 s19, s19
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s17, s22
; CHECK-NEXT: it vs
-; CHECK-NEXT: movvs r2, #0
-; CHECK-NEXT: lsrs r7, r1, #28
+; CHECK-NEXT: movvs.w r8, #0
+; CHECK-NEXT: and r5, r8, #15
+; CHECK-NEXT: vcmp.f32 s17, s22
+; CHECK-NEXT: lsrl r4, r5, #28
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vcmp.f32 s17, s20
-; CHECK-NEXT: orr.w r7, r7, r2, lsl #4
-; CHECK-NEXT: str r7, [r4, #20]
+; CHECK-NEXT: strb.w r4, [r9, #49]
; CHECK-NEXT: it lt
-; CHECK-NEXT: movlt r0, #0
+; CHECK-NEXT: mvnlt r3, #7
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vcmp.f32 s17, s17
; CHECK-NEXT: it gt
-; CHECK-NEXT: movgt.w r0, #-1
+; CHECK-NEXT: movgt r3, #7
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vcmp.f32 s17, s22
; CHECK-NEXT: it vs
-; CHECK-NEXT: movvs r0, #0
+; CHECK-NEXT: movvs r3, #0
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s17, s20
-; CHECK-NEXT: lsr.w r7, r0, #28
-; CHECK-NEXT: orr.w r1, r7, r1, lsl #4
-; CHECK-NEXT: str r1, [r4, #16]
; CHECK-NEXT: it lt
-; CHECK-NEXT: mvnlt r3, #7
+; CHECK-NEXT: movlt r1, #0
+; CHECK-NEXT: vcmp.f32 s17, s20
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s17, s17
; CHECK-NEXT: it gt
-; CHECK-NEXT: movgt r3, #7
+; CHECK-NEXT: movgt.w r1, #-1
+; CHECK-NEXT: vcmp.f32 s17, s17
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: lsr.w r1, r2, #28
-; CHECK-NEXT: vcmp.f32 s16, s22
; CHECK-NEXT: it vs
-; CHECK-NEXT: movvs r3, #0
-; CHECK-NEXT: orr.w r1, r1, r3, lsl #4
+; CHECK-NEXT: movvs r1, #0
+; CHECK-NEXT: vmov q0[3], q0[1], r1, r3
+; CHECK-NEXT: vcmp.f32 s17, s22
+; CHECK-NEXT: vmov r1, s1
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: strb r1, [r4, #24]
; CHECK-NEXT: it lt
-; CHECK-NEXT: mvnlt r5, #7
-; CHECK-NEXT: vcmp.f32 s16, s20
+; CHECK-NEXT: movlt r2, #0
+; CHECK-NEXT: vcmp.f32 s17, s20
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-NEXT: lsrl r0, r1, #28
; CHECK-NEXT: it gt
-; CHECK-NEXT: movgt r5, #7
-; CHECK-NEXT: vcmp.f32 s16, s16
+; CHECK-NEXT: movgt.w r2, #-1
+; CHECK-NEXT: vcmp.f32 s17, s17
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: it vs
-; CHECK-NEXT: movvs r5, #0
-; CHECK-NEXT: and r1, r5, #15
-; CHECK-NEXT: orr.w r0, r1, r0, lsl #4
-; CHECK-NEXT: str r0, [r4, #12]
+; CHECK-NEXT: movvs r2, #0
+; CHECK-NEXT: orr.w r1, r1, r2, lsl #4
+; CHECK-NEXT: strd r0, r1, [r9, #16]
+; CHECK-NEXT: and r1, r3, #15
+; CHECK-NEXT: lsrl r2, r1, #28
+; CHECK-NEXT: strb.w r2, [r9, #24]
; CHECK-NEXT: vpop {d8, d9, d10, d11}
; CHECK-NEXT: add sp, #4
-; CHECK-NEXT: pop {r4, r5, r6, r7, pc}
+; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, ...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/81261
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