[llvm] 9d00c34 - [AArch64] Extend and cleanup movi tests. NFC
David Green via llvm-commits
llvm-commits at lists.llvm.org
Sat Feb 3 13:23:05 PST 2024
Author: David Green
Date: 2024-02-03T21:23:01Z
New Revision: 9d00c3413299f537748e448e7197d6942c4651ea
URL: https://github.com/llvm/llvm-project/commit/9d00c3413299f537748e448e7197d6942c4651ea
DIFF: https://github.com/llvm/llvm-project/commit/9d00c3413299f537748e448e7197d6942c4651ea.diff
LOG: [AArch64] Extend and cleanup movi tests. NFC
Added:
Modified:
llvm/test/CodeGen/AArch64/neon-mov.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/AArch64/neon-mov.ll b/llvm/test/CodeGen/AArch64/neon-mov.ll
index 6ad98339e1477..219c8b53243e6 100644
--- a/llvm/test/CodeGen/AArch64/neon-mov.ll
+++ b/llvm/test/CodeGen/AArch64/neon-mov.ll
@@ -1,13 +1,31 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=+neon | FileCheck %s --check-prefixes=CHECK,CHECK-SD
-; RUN: llc -mtriple=aarch64-none-linux-gnu -mattr=+neon -global-isel %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-GI
+; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=+neon | FileCheck %s --check-prefixes=CHECK,CHECK-NOFP16,CHECK-NOFP16-SD
+; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=+neon,+fullfp16 | FileCheck %s --check-prefixes=CHECK,CHECK-FP16,CHECK-FP16-SD
+; RUN: llc -mtriple=aarch64-none-linux-gnu -mattr=+neon -global-isel %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-NOFP16,CHECK-NOFP16-GI
+; RUN: llc -mtriple=aarch64-none-linux-gnu -mattr=+neon,+fullfp16 -global-isel %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-FP16,CHECK-FP16-GI
+
+define <8 x i8> @movi8b_0() {
+; CHECK-LABEL: movi8b_0:
+; CHECK: // %bb.0:
+; CHECK-NEXT: movi v0.2d, #0000000000000000
+; CHECK-NEXT: ret
+ ret <8 x i8> zeroinitializer
+}
define <8 x i8> @movi8b() {
; CHECK-LABEL: movi8b:
; CHECK: // %bb.0:
; CHECK-NEXT: movi v0.8b, #8
; CHECK-NEXT: ret
- ret <8 x i8> < i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8 >
+ ret <8 x i8> <i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8>
+}
+
+define <16 x i8> @movi16b_0() {
+; CHECK-LABEL: movi16b_0:
+; CHECK: // %bb.0:
+; CHECK-NEXT: movi v0.2d, #0000000000000000
+; CHECK-NEXT: ret
+ ret <16 x i8> zeroinitializer
}
define <16 x i8> @movi16b() {
@@ -15,7 +33,15 @@ define <16 x i8> @movi16b() {
; CHECK: // %bb.0:
; CHECK-NEXT: movi v0.16b, #8
; CHECK-NEXT: ret
- ret <16 x i8> < i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8 >
+ ret <16 x i8> <i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8>
+}
+
+define <2 x i32> @movi2s_0() {
+; CHECK-LABEL: movi2s_0:
+; CHECK: // %bb.0:
+; CHECK-NEXT: movi v0.2d, #0000000000000000
+; CHECK-NEXT: ret
+ ret <2 x i32> zeroinitializer
}
define <2 x i32> @movi2s_lsl0() {
@@ -23,7 +49,7 @@ define <2 x i32> @movi2s_lsl0() {
; CHECK: // %bb.0:
; CHECK-NEXT: movi d0, #0x0000ff000000ff
; CHECK-NEXT: ret
- ret <2 x i32> < i32 255, i32 255 >
+ ret <2 x i32> <i32 255, i32 255>
}
define <2 x i32> @movi2s_lsl8() {
@@ -31,7 +57,7 @@ define <2 x i32> @movi2s_lsl8() {
; CHECK: // %bb.0:
; CHECK-NEXT: movi d0, #0x00ff000000ff00
; CHECK-NEXT: ret
- ret <2 x i32> < i32 65280, i32 65280 >
+ ret <2 x i32> <i32 65280, i32 65280>
}
define <2 x i32> @movi2s_lsl16() {
@@ -39,8 +65,7 @@ define <2 x i32> @movi2s_lsl16() {
; CHECK: // %bb.0:
; CHECK-NEXT: movi d0, #0xff000000ff0000
; CHECK-NEXT: ret
- ret <2 x i32> < i32 16711680, i32 16711680 >
-
+ ret <2 x i32> <i32 16711680, i32 16711680>
}
define <2 x i32> @movi2s_lsl24() {
@@ -48,7 +73,15 @@ define <2 x i32> @movi2s_lsl24() {
; CHECK: // %bb.0:
; CHECK-NEXT: movi d0, #0xff000000ff000000
; CHECK-NEXT: ret
- ret <2 x i32> < i32 4278190080, i32 4278190080 >
+ ret <2 x i32> <i32 4278190080, i32 4278190080>
+}
+
+define <4 x i32> @movi4s_0() {
+; CHECK-LABEL: movi4s_0:
+; CHECK: // %bb.0:
+; CHECK-NEXT: movi v0.2d, #0000000000000000
+; CHECK-NEXT: ret
+ ret <4 x i32> zeroinitializer
}
define <4 x i32> @movi4s_lsl0() {
@@ -56,7 +89,7 @@ define <4 x i32> @movi4s_lsl0() {
; CHECK: // %bb.0:
; CHECK-NEXT: movi v0.2d, #0x0000ff000000ff
; CHECK-NEXT: ret
- ret <4 x i32> < i32 255, i32 255, i32 255, i32 255 >
+ ret <4 x i32> <i32 255, i32 255, i32 255, i32 255>
}
define <4 x i32> @movi4s_lsl8() {
@@ -64,7 +97,7 @@ define <4 x i32> @movi4s_lsl8() {
; CHECK: // %bb.0:
; CHECK-NEXT: movi v0.2d, #0x00ff000000ff00
; CHECK-NEXT: ret
- ret <4 x i32> < i32 65280, i32 65280, i32 65280, i32 65280 >
+ ret <4 x i32> <i32 65280, i32 65280, i32 65280, i32 65280>
}
define <4 x i32> @movi4s_lsl16() {
@@ -72,8 +105,36 @@ define <4 x i32> @movi4s_lsl16() {
; CHECK: // %bb.0:
; CHECK-NEXT: movi v0.2d, #0xff000000ff0000
; CHECK-NEXT: ret
- ret <4 x i32> < i32 16711680, i32 16711680, i32 16711680, i32 16711680 >
+ ret <4 x i32> <i32 16711680, i32 16711680, i32 16711680, i32 16711680>
+}
+define <4 x i32> @movi4s_fneg() {
+; CHECK-NOFP16-SD-LABEL: movi4s_fneg:
+; CHECK-NOFP16-SD: // %bb.0:
+; CHECK-NOFP16-SD-NEXT: mov w8, #61440 // =0xf000
+; CHECK-NOFP16-SD-NEXT: movk w8, #32768, lsl #16
+; CHECK-NOFP16-SD-NEXT: dup v0.4s, w8
+; CHECK-NOFP16-SD-NEXT: ret
+;
+; CHECK-FP16-SD-LABEL: movi4s_fneg:
+; CHECK-FP16-SD: // %bb.0:
+; CHECK-FP16-SD-NEXT: mov w8, #61440 // =0xf000
+; CHECK-FP16-SD-NEXT: movk w8, #32768, lsl #16
+; CHECK-FP16-SD-NEXT: dup v0.4s, w8
+; CHECK-FP16-SD-NEXT: ret
+;
+; CHECK-NOFP16-GI-LABEL: movi4s_fneg:
+; CHECK-NOFP16-GI: // %bb.0:
+; CHECK-NOFP16-GI-NEXT: adrp x8, .LCPI13_0
+; CHECK-NOFP16-GI-NEXT: ldr q0, [x8, :lo12:.LCPI13_0]
+; CHECK-NOFP16-GI-NEXT: ret
+;
+; CHECK-FP16-GI-LABEL: movi4s_fneg:
+; CHECK-FP16-GI: // %bb.0:
+; CHECK-FP16-GI-NEXT: adrp x8, .LCPI13_0
+; CHECK-FP16-GI-NEXT: ldr q0, [x8, :lo12:.LCPI13_0]
+; CHECK-FP16-GI-NEXT: ret
+ ret <4 x i32> <i32 2147545088, i32 2147545088, i32 2147545088, i32 2147545088>
}
define <4 x i32> @movi4s_lsl24() {
@@ -81,7 +142,7 @@ define <4 x i32> @movi4s_lsl24() {
; CHECK: // %bb.0:
; CHECK-NEXT: movi v0.2d, #0xff000000ff000000
; CHECK-NEXT: ret
- ret <4 x i32> < i32 4278190080, i32 4278190080, i32 4278190080, i32 4278190080 >
+ ret <4 x i32> <i32 4278190080, i32 4278190080, i32 4278190080, i32 4278190080>
}
define <4 x i16> @movi4h_lsl0() {
@@ -89,7 +150,7 @@ define <4 x i16> @movi4h_lsl0() {
; CHECK: // %bb.0:
; CHECK-NEXT: movi d0, #0xff00ff00ff00ff
; CHECK-NEXT: ret
- ret <4 x i16> < i16 255, i16 255, i16 255, i16 255 >
+ ret <4 x i16> <i16 255, i16 255, i16 255, i16 255>
}
define <4 x i16> @movi4h_lsl8() {
@@ -97,7 +158,7 @@ define <4 x i16> @movi4h_lsl8() {
; CHECK: // %bb.0:
; CHECK-NEXT: movi d0, #0xff00ff00ff00ff00
; CHECK-NEXT: ret
- ret <4 x i16> < i16 65280, i16 65280, i16 65280, i16 65280 >
+ ret <4 x i16> <i16 65280, i16 65280, i16 65280, i16 65280>
}
define <8 x i16> @movi8h_lsl0() {
@@ -105,7 +166,7 @@ define <8 x i16> @movi8h_lsl0() {
; CHECK: // %bb.0:
; CHECK-NEXT: movi v0.2d, #0xff00ff00ff00ff
; CHECK-NEXT: ret
- ret <8 x i16> < i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255 >
+ ret <8 x i16> <i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255>
}
define <8 x i16> @movi8h_lsl8() {
@@ -113,7 +174,16 @@ define <8 x i16> @movi8h_lsl8() {
; CHECK: // %bb.0:
; CHECK-NEXT: movi v0.2d, #0xff00ff00ff00ff00
; CHECK-NEXT: ret
- ret <8 x i16> < i16 65280, i16 65280, i16 65280, i16 65280, i16 65280, i16 65280, i16 65280, i16 65280 >
+ ret <8 x i16> <i16 65280, i16 65280, i16 65280, i16 65280, i16 65280, i16 65280, i16 65280, i16 65280>
+}
+
+define <8 x i16> @movi8h_fneg() {
+; CHECK-LABEL: movi8h_fneg:
+; CHECK: // %bb.0:
+; CHECK-NEXT: adrp x8, .LCPI19_0
+; CHECK-NEXT: ldr q0, [x8, :lo12:.LCPI19_0]
+; CHECK-NEXT: ret
+ ret <8 x i16> <i16 32512, i16 65280, i16 32512, i16 65280, i16 32512, i16 65280, i16 32512, i16 65280>
}
@@ -122,7 +192,7 @@ define <2 x i32> @mvni2s_lsl0() {
; CHECK: // %bb.0:
; CHECK-NEXT: mvni v0.2s, #16
; CHECK-NEXT: ret
- ret <2 x i32> < i32 4294967279, i32 4294967279 >
+ ret <2 x i32> <i32 4294967279, i32 4294967279>
}
define <2 x i32> @mvni2s_lsl8() {
@@ -130,7 +200,7 @@ define <2 x i32> @mvni2s_lsl8() {
; CHECK: // %bb.0:
; CHECK-NEXT: mvni v0.2s, #16, lsl #8
; CHECK-NEXT: ret
- ret <2 x i32> < i32 4294963199, i32 4294963199 >
+ ret <2 x i32> <i32 4294963199, i32 4294963199>
}
define <2 x i32> @mvni2s_lsl16() {
@@ -138,7 +208,7 @@ define <2 x i32> @mvni2s_lsl16() {
; CHECK: // %bb.0:
; CHECK-NEXT: mvni v0.2s, #16, lsl #16
; CHECK-NEXT: ret
- ret <2 x i32> < i32 4293918719, i32 4293918719 >
+ ret <2 x i32> <i32 4293918719, i32 4293918719>
}
define <2 x i32> @mvni2s_lsl24() {
@@ -146,7 +216,7 @@ define <2 x i32> @mvni2s_lsl24() {
; CHECK: // %bb.0:
; CHECK-NEXT: mvni v0.2s, #16, lsl #24
; CHECK-NEXT: ret
- ret <2 x i32> < i32 4026531839, i32 4026531839 >
+ ret <2 x i32> <i32 4026531839, i32 4026531839>
}
define <4 x i32> @mvni4s_lsl0() {
@@ -154,7 +224,7 @@ define <4 x i32> @mvni4s_lsl0() {
; CHECK: // %bb.0:
; CHECK-NEXT: mvni v0.4s, #16
; CHECK-NEXT: ret
- ret <4 x i32> < i32 4294967279, i32 4294967279, i32 4294967279, i32 4294967279 >
+ ret <4 x i32> <i32 4294967279, i32 4294967279, i32 4294967279, i32 4294967279>
}
define <4 x i32> @mvni4s_lsl8() {
@@ -162,7 +232,7 @@ define <4 x i32> @mvni4s_lsl8() {
; CHECK: // %bb.0:
; CHECK-NEXT: mvni v0.4s, #16, lsl #8
; CHECK-NEXT: ret
- ret <4 x i32> < i32 4294963199, i32 4294963199, i32 4294963199, i32 4294963199 >
+ ret <4 x i32> <i32 4294963199, i32 4294963199, i32 4294963199, i32 4294963199>
}
define <4 x i32> @mvni4s_lsl16() {
@@ -170,7 +240,7 @@ define <4 x i32> @mvni4s_lsl16() {
; CHECK: // %bb.0:
; CHECK-NEXT: mvni v0.4s, #16, lsl #16
; CHECK-NEXT: ret
- ret <4 x i32> < i32 4293918719, i32 4293918719, i32 4293918719, i32 4293918719 >
+ ret <4 x i32> <i32 4293918719, i32 4293918719, i32 4293918719, i32 4293918719>
}
@@ -179,7 +249,7 @@ define <4 x i32> @mvni4s_lsl24() {
; CHECK: // %bb.0:
; CHECK-NEXT: mvni v0.4s, #16, lsl #24
; CHECK-NEXT: ret
- ret <4 x i32> < i32 4026531839, i32 4026531839, i32 4026531839, i32 4026531839 >
+ ret <4 x i32> <i32 4026531839, i32 4026531839, i32 4026531839, i32 4026531839>
}
@@ -188,7 +258,7 @@ define <4 x i16> @mvni4h_lsl0() {
; CHECK: // %bb.0:
; CHECK-NEXT: mvni v0.4h, #16
; CHECK-NEXT: ret
- ret <4 x i16> < i16 65519, i16 65519, i16 65519, i16 65519 >
+ ret <4 x i16> <i16 65519, i16 65519, i16 65519, i16 65519>
}
define <4 x i16> @mvni4h_lsl8() {
@@ -196,7 +266,7 @@ define <4 x i16> @mvni4h_lsl8() {
; CHECK: // %bb.0:
; CHECK-NEXT: mvni v0.4h, #16, lsl #8
; CHECK-NEXT: ret
- ret <4 x i16> < i16 61439, i16 61439, i16 61439, i16 61439 >
+ ret <4 x i16> <i16 61439, i16 61439, i16 61439, i16 61439>
}
define <8 x i16> @mvni8h_lsl0() {
@@ -204,7 +274,7 @@ define <8 x i16> @mvni8h_lsl0() {
; CHECK: // %bb.0:
; CHECK-NEXT: mvni v0.8h, #16
; CHECK-NEXT: ret
- ret <8 x i16> < i16 65519, i16 65519, i16 65519, i16 65519, i16 65519, i16 65519, i16 65519, i16 65519 >
+ ret <8 x i16> <i16 65519, i16 65519, i16 65519, i16 65519, i16 65519, i16 65519, i16 65519, i16 65519>
}
define <8 x i16> @mvni8h_lsl8() {
@@ -212,7 +282,34 @@ define <8 x i16> @mvni8h_lsl8() {
; CHECK: // %bb.0:
; CHECK-NEXT: mvni v0.8h, #16, lsl #8
; CHECK-NEXT: ret
- ret <8 x i16> < i16 61439, i16 61439, i16 61439, i16 61439, i16 61439, i16 61439, i16 61439, i16 61439 >
+ ret <8 x i16> <i16 61439, i16 61439, i16 61439, i16 61439, i16 61439, i16 61439, i16 61439, i16 61439>
+}
+
+define <8 x i16> @mvni8h_neg() {
+; CHECK-NOFP16-SD-LABEL: mvni8h_neg:
+; CHECK-NOFP16-SD: // %bb.0:
+; CHECK-NOFP16-SD-NEXT: mov w8, #33008 // =0x80f0
+; CHECK-NOFP16-SD-NEXT: dup v0.8h, w8
+; CHECK-NOFP16-SD-NEXT: ret
+;
+; CHECK-FP16-SD-LABEL: mvni8h_neg:
+; CHECK-FP16-SD: // %bb.0:
+; CHECK-FP16-SD-NEXT: mov w8, #33008 // =0x80f0
+; CHECK-FP16-SD-NEXT: dup v0.8h, w8
+; CHECK-FP16-SD-NEXT: ret
+;
+; CHECK-NOFP16-GI-LABEL: mvni8h_neg:
+; CHECK-NOFP16-GI: // %bb.0:
+; CHECK-NOFP16-GI-NEXT: adrp x8, .LCPI32_0
+; CHECK-NOFP16-GI-NEXT: ldr q0, [x8, :lo12:.LCPI32_0]
+; CHECK-NOFP16-GI-NEXT: ret
+;
+; CHECK-FP16-GI-LABEL: mvni8h_neg:
+; CHECK-FP16-GI: // %bb.0:
+; CHECK-FP16-GI-NEXT: adrp x8, .LCPI32_0
+; CHECK-FP16-GI-NEXT: ldr q0, [x8, :lo12:.LCPI32_0]
+; CHECK-FP16-GI-NEXT: ret
+ ret <8 x i16> <i16 33008, i16 33008, i16 33008, i16 33008, i16 33008, i16 33008, i16 33008, i16 33008>
}
@@ -221,7 +318,7 @@ define <2 x i32> @movi2s_msl8(<2 x i32> %a) {
; CHECK: // %bb.0:
; CHECK-NEXT: movi d0, #0x00ffff0000ffff
; CHECK-NEXT: ret
- ret <2 x i32> < i32 65535, i32 65535 >
+ ret <2 x i32> <i32 65535, i32 65535>
}
define <2 x i32> @movi2s_msl16() {
@@ -229,7 +326,7 @@ define <2 x i32> @movi2s_msl16() {
; CHECK: // %bb.0:
; CHECK-NEXT: movi d0, #0xffffff00ffffff
; CHECK-NEXT: ret
- ret <2 x i32> < i32 16777215, i32 16777215 >
+ ret <2 x i32> <i32 16777215, i32 16777215>
}
@@ -238,7 +335,7 @@ define <4 x i32> @movi4s_msl8() {
; CHECK: // %bb.0:
; CHECK-NEXT: movi v0.2d, #0x00ffff0000ffff
; CHECK-NEXT: ret
- ret <4 x i32> < i32 65535, i32 65535, i32 65535, i32 65535 >
+ ret <4 x i32> <i32 65535, i32 65535, i32 65535, i32 65535>
}
define <4 x i32> @movi4s_msl16() {
@@ -246,7 +343,7 @@ define <4 x i32> @movi4s_msl16() {
; CHECK: // %bb.0:
; CHECK-NEXT: movi v0.2d, #0xffffff00ffffff
; CHECK-NEXT: ret
- ret <4 x i32> < i32 16777215, i32 16777215, i32 16777215, i32 16777215 >
+ ret <4 x i32> <i32 16777215, i32 16777215, i32 16777215, i32 16777215>
}
define <2 x i32> @mvni2s_msl8() {
@@ -254,7 +351,7 @@ define <2 x i32> @mvni2s_msl8() {
; CHECK: // %bb.0:
; CHECK-NEXT: mvni v0.2s, #16, msl #8
; CHECK-NEXT: ret
- ret <2 x i32> < i32 18446744073709547264, i32 18446744073709547264>
+ ret <2 x i32> <i32 18446744073709547264, i32 18446744073709547264>
}
define <2 x i32> @mvni2s_msl16() {
@@ -262,7 +359,7 @@ define <2 x i32> @mvni2s_msl16() {
; CHECK: // %bb.0:
; CHECK-NEXT: mvni v0.2s, #16, msl #16
; CHECK-NEXT: ret
- ret <2 x i32> < i32 18446744073708437504, i32 18446744073708437504>
+ ret <2 x i32> <i32 18446744073708437504, i32 18446744073708437504>
}
define <4 x i32> @mvni4s_msl8() {
@@ -270,7 +367,7 @@ define <4 x i32> @mvni4s_msl8() {
; CHECK: // %bb.0:
; CHECK-NEXT: mvni v0.4s, #16, msl #8
; CHECK-NEXT: ret
- ret <4 x i32> < i32 18446744073709547264, i32 18446744073709547264, i32 18446744073709547264, i32 18446744073709547264>
+ ret <4 x i32> <i32 18446744073709547264, i32 18446744073709547264, i32 18446744073709547264, i32 18446744073709547264>
}
define <4 x i32> @mvni4s_msl16() {
@@ -278,7 +375,7 @@ define <4 x i32> @mvni4s_msl16() {
; CHECK: // %bb.0:
; CHECK-NEXT: mvni v0.4s, #16, msl #16
; CHECK-NEXT: ret
- ret <4 x i32> < i32 18446744073708437504, i32 18446744073708437504, i32 18446744073708437504, i32 18446744073708437504>
+ ret <4 x i32> <i32 18446744073708437504, i32 18446744073708437504, i32 18446744073708437504, i32 18446744073708437504>
}
define <2 x i64> @movi2d() {
@@ -286,22 +383,42 @@ define <2 x i64> @movi2d() {
; CHECK: // %bb.0:
; CHECK-NEXT: movi v0.2d, #0xff0000ff0000ffff
; CHECK-NEXT: ret
- ret <2 x i64> < i64 18374687574888349695, i64 18374687574888349695 >
+ ret <2 x i64> <i64 18374687574888349695, i64 18374687574888349695>
}
define <1 x i64> @movid() {
-; CHECK-SD-LABEL: movid:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: movi d0, #0xff0000ff0000ffff
-; CHECK-SD-NEXT: ret
+; CHECK-NOFP16-SD-LABEL: movid:
+; CHECK-NOFP16-SD: // %bb.0:
+; CHECK-NOFP16-SD-NEXT: movi d0, #0xff0000ff0000ffff
+; CHECK-NOFP16-SD-NEXT: ret
+;
+; CHECK-FP16-SD-LABEL: movid:
+; CHECK-FP16-SD: // %bb.0:
+; CHECK-FP16-SD-NEXT: movi d0, #0xff0000ff0000ffff
+; CHECK-FP16-SD-NEXT: ret
;
-; CHECK-GI-LABEL: movid:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: mov x8, #-72056494526300161 // =0xff0000ffffffffff
-; CHECK-GI-NEXT: movk x8, #0, lsl #16
-; CHECK-GI-NEXT: fmov d0, x8
-; CHECK-GI-NEXT: ret
- ret <1 x i64> < i64 18374687574888349695 >
+; CHECK-NOFP16-GI-LABEL: movid:
+; CHECK-NOFP16-GI: // %bb.0:
+; CHECK-NOFP16-GI-NEXT: mov x8, #-72056494526300161 // =0xff0000ffffffffff
+; CHECK-NOFP16-GI-NEXT: movk x8, #0, lsl #16
+; CHECK-NOFP16-GI-NEXT: fmov d0, x8
+; CHECK-NOFP16-GI-NEXT: ret
+;
+; CHECK-FP16-GI-LABEL: movid:
+; CHECK-FP16-GI: // %bb.0:
+; CHECK-FP16-GI-NEXT: mov x8, #-72056494526300161 // =0xff0000ffffffffff
+; CHECK-FP16-GI-NEXT: movk x8, #0, lsl #16
+; CHECK-FP16-GI-NEXT: fmov d0, x8
+; CHECK-FP16-GI-NEXT: ret
+ ret <1 x i64> <i64 18374687574888349695>
+}
+
+define <2 x float> @fmov2s_0() {
+; CHECK-LABEL: fmov2s_0:
+; CHECK: // %bb.0:
+; CHECK-NEXT: movi v0.2d, #0000000000000000
+; CHECK-NEXT: ret
+ ret <2 x float> zeroinitializer
}
define <2 x float> @fmov2s() {
@@ -309,7 +426,23 @@ define <2 x float> @fmov2s() {
; CHECK: // %bb.0:
; CHECK-NEXT: fmov v0.2s, #-12.00000000
; CHECK-NEXT: ret
- ret <2 x float> < float -1.2e1, float -1.2e1>
+ ret <2 x float> <float -1.2e1, float -1.2e1>
+}
+
+define <2 x float> @fmov2s_neg0() {
+; CHECK-LABEL: fmov2s_neg0:
+; CHECK: // %bb.0:
+; CHECK-NEXT: movi v0.2s, #128, lsl #24
+; CHECK-NEXT: ret
+ ret <2 x float> <float -0.0, float -0.0>
+}
+
+define <4 x float> @fmov4s_0() {
+; CHECK-LABEL: fmov4s_0:
+; CHECK: // %bb.0:
+; CHECK-NEXT: movi v0.2d, #0000000000000000
+; CHECK-NEXT: ret
+ ret <4 x float> zeroinitializer
}
define <4 x float> @fmov4s() {
@@ -317,7 +450,23 @@ define <4 x float> @fmov4s() {
; CHECK: // %bb.0:
; CHECK-NEXT: fmov v0.4s, #-12.00000000
; CHECK-NEXT: ret
- ret <4 x float> < float -1.2e1, float -1.2e1, float -1.2e1, float -1.2e1>
+ ret <4 x float> <float -1.2e1, float -1.2e1, float -1.2e1, float -1.2e1>
+}
+
+define <4 x float> @fmov4s_neg0() {
+; CHECK-LABEL: fmov4s_neg0:
+; CHECK: // %bb.0:
+; CHECK-NEXT: movi v0.4s, #128, lsl #24
+; CHECK-NEXT: ret
+ ret <4 x float> <float -0.0, float -0.0, float -0.0, float -0.0>
+}
+
+define <2 x double> @fmov2d_0() {
+; CHECK-LABEL: fmov2d_0:
+; CHECK: // %bb.0:
+; CHECK-NEXT: movi v0.2d, #0000000000000000
+; CHECK-NEXT: ret
+ ret <2 x double> zeroinitializer
}
define <2 x double> @fmov2d() {
@@ -325,41 +474,96 @@ define <2 x double> @fmov2d() {
; CHECK: // %bb.0:
; CHECK-NEXT: fmov v0.2d, #-12.00000000
; CHECK-NEXT: ret
- ret <2 x double> < double -1.2e1, double -1.2e1>
+ ret <2 x double> <double -1.2e1, double -1.2e1>
+}
+
+define <2 x double> @fmov2d_neg0() {
+; CHECK-NOFP16-SD-LABEL: fmov2d_neg0:
+; CHECK-NOFP16-SD: // %bb.0:
+; CHECK-NOFP16-SD-NEXT: mov x8, #-9223372036854775808 // =0x8000000000000000
+; CHECK-NOFP16-SD-NEXT: dup v0.2d, x8
+; CHECK-NOFP16-SD-NEXT: ret
+;
+; CHECK-FP16-SD-LABEL: fmov2d_neg0:
+; CHECK-FP16-SD: // %bb.0:
+; CHECK-FP16-SD-NEXT: mov x8, #-9223372036854775808 // =0x8000000000000000
+; CHECK-FP16-SD-NEXT: dup v0.2d, x8
+; CHECK-FP16-SD-NEXT: ret
+;
+; CHECK-NOFP16-GI-LABEL: fmov2d_neg0:
+; CHECK-NOFP16-GI: // %bb.0:
+; CHECK-NOFP16-GI-NEXT: adrp x8, .LCPI51_0
+; CHECK-NOFP16-GI-NEXT: ldr q0, [x8, :lo12:.LCPI51_0]
+; CHECK-NOFP16-GI-NEXT: ret
+;
+; CHECK-FP16-GI-LABEL: fmov2d_neg0:
+; CHECK-FP16-GI: // %bb.0:
+; CHECK-FP16-GI-NEXT: adrp x8, .LCPI51_0
+; CHECK-FP16-GI-NEXT: ldr q0, [x8, :lo12:.LCPI51_0]
+; CHECK-FP16-GI-NEXT: ret
+ ret <2 x double> <double -0.0, double -0.0>
}
define <2 x i32> @movi1d_1() {
-; CHECK-SD-LABEL: movi1d_1:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: movi d0, #0x00ffffffff0000
-; CHECK-SD-NEXT: ret
+; CHECK-NOFP16-SD-LABEL: movi1d_1:
+; CHECK-NOFP16-SD: // %bb.0:
+; CHECK-NOFP16-SD-NEXT: movi d0, #0x00ffffffff0000
+; CHECK-NOFP16-SD-NEXT: ret
+;
+; CHECK-FP16-SD-LABEL: movi1d_1:
+; CHECK-FP16-SD: // %bb.0:
+; CHECK-FP16-SD-NEXT: movi d0, #0x00ffffffff0000
+; CHECK-FP16-SD-NEXT: ret
+;
+; CHECK-NOFP16-GI-LABEL: movi1d_1:
+; CHECK-NOFP16-GI: // %bb.0:
+; CHECK-NOFP16-GI-NEXT: adrp x8, .LCPI52_0
+; CHECK-NOFP16-GI-NEXT: ldr d0, [x8, :lo12:.LCPI52_0]
+; CHECK-NOFP16-GI-NEXT: ret
;
-; CHECK-GI-LABEL: movi1d_1:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: adrp x8, .LCPI39_0
-; CHECK-GI-NEXT: ldr d0, [x8, :lo12:.LCPI39_0]
-; CHECK-GI-NEXT: ret
- ret <2 x i32> < i32 -65536, i32 65535>
+; CHECK-FP16-GI-LABEL: movi1d_1:
+; CHECK-FP16-GI: // %bb.0:
+; CHECK-FP16-GI-NEXT: adrp x8, .LCPI52_0
+; CHECK-FP16-GI-NEXT: ldr d0, [x8, :lo12:.LCPI52_0]
+; CHECK-FP16-GI-NEXT: ret
+ ret <2 x i32> <i32 -65536, i32 65535>
}
declare <2 x i32> @test_movi1d(<2 x i32>, <2 x i32>)
define <2 x i32> @movi1d() {
-; CHECK-SD-LABEL: movi1d:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: movi d1, #0x00ffffffff0000
-; CHECK-SD-NEXT: adrp x8, .LCPI40_0
-; CHECK-SD-NEXT: ldr d0, [x8, :lo12:.LCPI40_0]
-; CHECK-SD-NEXT: b test_movi1d
+; CHECK-NOFP16-SD-LABEL: movi1d:
+; CHECK-NOFP16-SD: // %bb.0:
+; CHECK-NOFP16-SD-NEXT: movi d1, #0x00ffffffff0000
+; CHECK-NOFP16-SD-NEXT: adrp x8, .LCPI53_0
+; CHECK-NOFP16-SD-NEXT: ldr d0, [x8, :lo12:.LCPI53_0]
+; CHECK-NOFP16-SD-NEXT: b test_movi1d
;
-; CHECK-GI-LABEL: movi1d:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: adrp x8, .LCPI40_1
-; CHECK-GI-NEXT: adrp x9, .LCPI40_0
-; CHECK-GI-NEXT: ldr d0, [x8, :lo12:.LCPI40_1]
-; CHECK-GI-NEXT: ldr d1, [x9, :lo12:.LCPI40_0]
-; CHECK-GI-NEXT: b test_movi1d
+; CHECK-FP16-SD-LABEL: movi1d:
+; CHECK-FP16-SD: // %bb.0:
+; CHECK-FP16-SD-NEXT: movi d1, #0x00ffffffff0000
+; CHECK-FP16-SD-NEXT: adrp x8, .LCPI53_0
+; CHECK-FP16-SD-NEXT: ldr d0, [x8, :lo12:.LCPI53_0]
+; CHECK-FP16-SD-NEXT: b test_movi1d
+;
+; CHECK-NOFP16-GI-LABEL: movi1d:
+; CHECK-NOFP16-GI: // %bb.0:
+; CHECK-NOFP16-GI-NEXT: adrp x8, .LCPI53_1
+; CHECK-NOFP16-GI-NEXT: adrp x9, .LCPI53_0
+; CHECK-NOFP16-GI-NEXT: ldr d0, [x8, :lo12:.LCPI53_1]
+; CHECK-NOFP16-GI-NEXT: ldr d1, [x9, :lo12:.LCPI53_0]
+; CHECK-NOFP16-GI-NEXT: b test_movi1d
+;
+; CHECK-FP16-GI-LABEL: movi1d:
+; CHECK-FP16-GI: // %bb.0:
+; CHECK-FP16-GI-NEXT: adrp x8, .LCPI53_1
+; CHECK-FP16-GI-NEXT: adrp x9, .LCPI53_0
+; CHECK-FP16-GI-NEXT: ldr d0, [x8, :lo12:.LCPI53_1]
+; CHECK-FP16-GI-NEXT: ldr d1, [x9, :lo12:.LCPI53_0]
+; CHECK-FP16-GI-NEXT: b test_movi1d
%1 = tail call <2 x i32> @test_movi1d(<2 x i32> <i32 -2147483648, i32 2147450880>, <2 x i32> <i32 -65536, i32 65535>)
ret <2 x i32> %1
}
-
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; CHECK-FP16: {{.*}}
+; CHECK-NOFP16: {{.*}}
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