[llvm] 08e942a - [RISCV] Combine (xor (trunc (X cc Y)) 1) -> (trunc (X !cc Y)) for RV64LegalI32.
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Sat Feb 3 14:01:46 PST 2024
Author: Craig Topper
Date: 2024-02-03T13:57:47-08:00
New Revision: 08e942aca64d4d16e55a25d7e7eda8ef192727fd
URL: https://github.com/llvm/llvm-project/commit/08e942aca64d4d16e55a25d7e7eda8ef192727fd
DIFF: https://github.com/llvm/llvm-project/commit/08e942aca64d4d16e55a25d7e7eda8ef192727fd.diff
LOG: [RISCV] Combine (xor (trunc (X cc Y)) 1) -> (trunc (X !cc Y)) for RV64LegalI32.
This is needed with RV64LegalI32 when the setcc is created after type
legalization. An i1 xor would have been promoted to i32, but the setcc
would have i64 result.
Added:
Modified:
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
llvm/test/CodeGen/RISCV/rv64-legal-i32/xaluo.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index fead2aebb5830..b4bde4c5dd5dd 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -12933,6 +12933,23 @@ static SDValue performXORCombine(SDNode *N, SelectionDAG &DAG,
}
}
+ // Combine (xor (trunc (X cc Y)) 1) -> (trunc (X !cc Y)). This is needed with
+ // RV64LegalI32 when the setcc is created after type legalization. An i1 xor
+ // would have been promoted to i32, but the setcc would have i64 result.
+ if (N->getValueType(0) == MVT::i32 && N0.getOpcode() == ISD::TRUNCATE &&
+ isOneConstant(N1) && N0.getOperand(0).getOpcode() == ISD::SETCC) {
+ SDValue N00 = N0.getOperand(0);
+ SDLoc DL(N);
+ SDValue LHS = N00.getOperand(0);
+ SDValue RHS = N00.getOperand(1);
+ SDValue CC = N00.getOperand(2);
+ ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
+ LHS.getValueType());
+ SDValue Setcc = DAG.getSetCC(SDLoc(N00), N0.getOperand(0).getValueType(),
+ LHS, RHS, NotCC);
+ return DAG.getNode(ISD::TRUNCATE, SDLoc(N0), N->getValueType(0), Setcc);
+ }
+
if (SDValue V = combineBinOpToReduce(N, DAG, Subtarget))
return V;
if (SDValue V = combineBinOpOfExtractToReduceTree(N, DAG, Subtarget))
diff --git a/llvm/test/CodeGen/RISCV/rv64-legal-i32/xaluo.ll b/llvm/test/CodeGen/RISCV/rv64-legal-i32/xaluo.ll
index 304093bf23fd8..3c1b76818781a 100644
--- a/llvm/test/CodeGen/RISCV/rv64-legal-i32/xaluo.ll
+++ b/llvm/test/CodeGen/RISCV/rv64-legal-i32/xaluo.ll
@@ -997,8 +997,7 @@ define i1 @saddo.not.i32(i32 signext %v1, i32 signext %v2) {
; RV64-NEXT: addw a2, a0, a1
; RV64-NEXT: add a0, a0, a1
; RV64-NEXT: xor a0, a0, a2
-; RV64-NEXT: snez a0, a0
-; RV64-NEXT: xori a0, a0, 1
+; RV64-NEXT: seqz a0, a0
; RV64-NEXT: ret
;
; RV64ZBA-LABEL: saddo.not.i32:
@@ -1006,8 +1005,7 @@ define i1 @saddo.not.i32(i32 signext %v1, i32 signext %v2) {
; RV64ZBA-NEXT: addw a2, a0, a1
; RV64ZBA-NEXT: add a0, a0, a1
; RV64ZBA-NEXT: xor a0, a0, a2
-; RV64ZBA-NEXT: snez a0, a0
-; RV64ZBA-NEXT: xori a0, a0, 1
+; RV64ZBA-NEXT: seqz a0, a0
; RV64ZBA-NEXT: ret
;
; RV64ZICOND-LABEL: saddo.not.i32:
@@ -1015,8 +1013,7 @@ define i1 @saddo.not.i32(i32 signext %v1, i32 signext %v2) {
; RV64ZICOND-NEXT: addw a2, a0, a1
; RV64ZICOND-NEXT: add a0, a0, a1
; RV64ZICOND-NEXT: xor a0, a0, a2
-; RV64ZICOND-NEXT: snez a0, a0
-; RV64ZICOND-NEXT: xori a0, a0, 1
+; RV64ZICOND-NEXT: seqz a0, a0
; RV64ZICOND-NEXT: ret
entry:
%t = call {i32, i1} @llvm.sadd.with.overflow.i32(i32 %v1, i32 %v2)
@@ -1266,8 +1263,7 @@ define i1 @ssubo.not.i32(i32 signext %v1, i32 signext %v2) {
; RV64-NEXT: subw a2, a0, a1
; RV64-NEXT: sub a0, a0, a1
; RV64-NEXT: xor a0, a0, a2
-; RV64-NEXT: snez a0, a0
-; RV64-NEXT: xori a0, a0, 1
+; RV64-NEXT: seqz a0, a0
; RV64-NEXT: ret
;
; RV64ZBA-LABEL: ssubo.not.i32:
@@ -1275,8 +1271,7 @@ define i1 @ssubo.not.i32(i32 signext %v1, i32 signext %v2) {
; RV64ZBA-NEXT: subw a2, a0, a1
; RV64ZBA-NEXT: sub a0, a0, a1
; RV64ZBA-NEXT: xor a0, a0, a2
-; RV64ZBA-NEXT: snez a0, a0
-; RV64ZBA-NEXT: xori a0, a0, 1
+; RV64ZBA-NEXT: seqz a0, a0
; RV64ZBA-NEXT: ret
;
; RV64ZICOND-LABEL: ssubo.not.i32:
@@ -1284,8 +1279,7 @@ define i1 @ssubo.not.i32(i32 signext %v1, i32 signext %v2) {
; RV64ZICOND-NEXT: subw a2, a0, a1
; RV64ZICOND-NEXT: sub a0, a0, a1
; RV64ZICOND-NEXT: xor a0, a0, a2
-; RV64ZICOND-NEXT: snez a0, a0
-; RV64ZICOND-NEXT: xori a0, a0, 1
+; RV64ZICOND-NEXT: seqz a0, a0
; RV64ZICOND-NEXT: ret
entry:
%t = call {i32, i1} @llvm.ssub.with.overflow.i32(i32 %v1, i32 %v2)
@@ -1535,8 +1529,7 @@ define i1 @smulo.not.i32(i32 signext %v1, i32 signext %v2) {
; RV64-NEXT: mulw a2, a0, a1
; RV64-NEXT: mul a0, a0, a1
; RV64-NEXT: xor a0, a0, a2
-; RV64-NEXT: snez a0, a0
-; RV64-NEXT: xori a0, a0, 1
+; RV64-NEXT: seqz a0, a0
; RV64-NEXT: ret
;
; RV64ZBA-LABEL: smulo.not.i32:
@@ -1544,8 +1537,7 @@ define i1 @smulo.not.i32(i32 signext %v1, i32 signext %v2) {
; RV64ZBA-NEXT: mulw a2, a0, a1
; RV64ZBA-NEXT: mul a0, a0, a1
; RV64ZBA-NEXT: xor a0, a0, a2
-; RV64ZBA-NEXT: snez a0, a0
-; RV64ZBA-NEXT: xori a0, a0, 1
+; RV64ZBA-NEXT: seqz a0, a0
; RV64ZBA-NEXT: ret
;
; RV64ZICOND-LABEL: smulo.not.i32:
@@ -1553,8 +1545,7 @@ define i1 @smulo.not.i32(i32 signext %v1, i32 signext %v2) {
; RV64ZICOND-NEXT: mulw a2, a0, a1
; RV64ZICOND-NEXT: mul a0, a0, a1
; RV64ZICOND-NEXT: xor a0, a0, a2
-; RV64ZICOND-NEXT: snez a0, a0
-; RV64ZICOND-NEXT: xori a0, a0, 1
+; RV64ZICOND-NEXT: seqz a0, a0
; RV64ZICOND-NEXT: ret
entry:
%t = call {i32, i1} @llvm.smul.with.overflow.i32(i32 %v1, i32 %v2)
@@ -1610,8 +1601,7 @@ define i1 @smulo.not.i64(i64 %v1, i64 %v2) {
; RV64-NEXT: mul a0, a0, a1
; RV64-NEXT: srai a0, a0, 63
; RV64-NEXT: xor a0, a2, a0
-; RV64-NEXT: snez a0, a0
-; RV64-NEXT: xori a0, a0, 1
+; RV64-NEXT: seqz a0, a0
; RV64-NEXT: ret
;
; RV64ZBA-LABEL: smulo.not.i64:
@@ -1620,8 +1610,7 @@ define i1 @smulo.not.i64(i64 %v1, i64 %v2) {
; RV64ZBA-NEXT: mul a0, a0, a1
; RV64ZBA-NEXT: srai a0, a0, 63
; RV64ZBA-NEXT: xor a0, a2, a0
-; RV64ZBA-NEXT: snez a0, a0
-; RV64ZBA-NEXT: xori a0, a0, 1
+; RV64ZBA-NEXT: seqz a0, a0
; RV64ZBA-NEXT: ret
;
; RV64ZICOND-LABEL: smulo.not.i64:
@@ -1630,8 +1619,7 @@ define i1 @smulo.not.i64(i64 %v1, i64 %v2) {
; RV64ZICOND-NEXT: mul a0, a0, a1
; RV64ZICOND-NEXT: srai a0, a0, 63
; RV64ZICOND-NEXT: xor a0, a2, a0
-; RV64ZICOND-NEXT: snez a0, a0
-; RV64ZICOND-NEXT: xori a0, a0, 1
+; RV64ZICOND-NEXT: seqz a0, a0
; RV64ZICOND-NEXT: ret
entry:
%t = call {i64, i1} @llvm.smul.with.overflow.i64(i64 %v1, i64 %v2)
@@ -1689,8 +1677,7 @@ define i1 @umulo.not.i32(i32 signext %v1, i32 signext %v2) {
; RV64-NEXT: slli a0, a0, 32
; RV64-NEXT: mulhu a0, a0, a1
; RV64-NEXT: srai a0, a0, 32
-; RV64-NEXT: snez a0, a0
-; RV64-NEXT: xori a0, a0, 1
+; RV64-NEXT: seqz a0, a0
; RV64-NEXT: ret
;
; RV64ZBA-LABEL: umulo.not.i32:
@@ -1699,8 +1686,7 @@ define i1 @umulo.not.i32(i32 signext %v1, i32 signext %v2) {
; RV64ZBA-NEXT: zext.w a0, a0
; RV64ZBA-NEXT: mul a0, a0, a1
; RV64ZBA-NEXT: srai a0, a0, 32
-; RV64ZBA-NEXT: snez a0, a0
-; RV64ZBA-NEXT: xori a0, a0, 1
+; RV64ZBA-NEXT: seqz a0, a0
; RV64ZBA-NEXT: ret
;
; RV64ZICOND-LABEL: umulo.not.i32:
@@ -1709,8 +1695,7 @@ define i1 @umulo.not.i32(i32 signext %v1, i32 signext %v2) {
; RV64ZICOND-NEXT: slli a0, a0, 32
; RV64ZICOND-NEXT: mulhu a0, a0, a1
; RV64ZICOND-NEXT: srai a0, a0, 32
-; RV64ZICOND-NEXT: snez a0, a0
-; RV64ZICOND-NEXT: xori a0, a0, 1
+; RV64ZICOND-NEXT: seqz a0, a0
; RV64ZICOND-NEXT: ret
entry:
%t = call {i32, i1} @llvm.umul.with.overflow.i32(i32 %v1, i32 %v2)
@@ -1756,22 +1741,19 @@ define i1 @umulo.not.i64(i64 %v1, i64 %v2) {
; RV64-LABEL: umulo.not.i64:
; RV64: # %bb.0: # %entry
; RV64-NEXT: mulhu a0, a0, a1
-; RV64-NEXT: snez a0, a0
-; RV64-NEXT: xori a0, a0, 1
+; RV64-NEXT: seqz a0, a0
; RV64-NEXT: ret
;
; RV64ZBA-LABEL: umulo.not.i64:
; RV64ZBA: # %bb.0: # %entry
; RV64ZBA-NEXT: mulhu a0, a0, a1
-; RV64ZBA-NEXT: snez a0, a0
-; RV64ZBA-NEXT: xori a0, a0, 1
+; RV64ZBA-NEXT: seqz a0, a0
; RV64ZBA-NEXT: ret
;
; RV64ZICOND-LABEL: umulo.not.i64:
; RV64ZICOND: # %bb.0: # %entry
; RV64ZICOND-NEXT: mulhu a0, a0, a1
-; RV64ZICOND-NEXT: snez a0, a0
-; RV64ZICOND-NEXT: xori a0, a0, 1
+; RV64ZICOND-NEXT: seqz a0, a0
; RV64ZICOND-NEXT: ret
entry:
%t = call {i64, i1} @llvm.umul.with.overflow.i64(i64 %v1, i64 %v2)
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