[llvm] ea59b15 - [RISCV] Add more RUN lines to rv64-legal-i32/xaluo.ll. NFC
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Sat Feb 3 13:15:07 PST 2024
Author: Craig Topper
Date: 2024-02-03T13:11:59-08:00
New Revision: ea59b15cf70b53f6a4f3ba0d495d0566a0e77e44
URL: https://github.com/llvm/llvm-project/commit/ea59b15cf70b53f6a4f3ba0d495d0566a0e77e44
DIFF: https://github.com/llvm/llvm-project/commit/ea59b15cf70b53f6a4f3ba0d495d0566a0e77e44.diff
LOG: [RISCV] Add more RUN lines to rv64-legal-i32/xaluo.ll. NFC
This matches the non-rv64-legal-i32 version.
Added:
Modified:
llvm/test/CodeGen/RISCV/rv64-legal-i32/xaluo.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/RISCV/rv64-legal-i32/xaluo.ll b/llvm/test/CodeGen/RISCV/rv64-legal-i32/xaluo.ll
index a58fd6f785411..304093bf23fd8 100644
--- a/llvm/test/CodeGen/RISCV/rv64-legal-i32/xaluo.ll
+++ b/llvm/test/CodeGen/RISCV/rv64-legal-i32/xaluo.ll
@@ -1,6 +1,10 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv64 -mattr=+m -verify-machineinstrs < %s \
+; RUN: llc < %s -mtriple=riscv64 -mattr=+m -verify-machineinstrs \
; RUN: -riscv-experimental-rv64-legal-i32 | FileCheck %s -check-prefix=RV64
+; RUN: llc < %s -mtriple=riscv64 -mattr=+m,+zba -verify-machineinstrs \
+; RUN: -riscv-experimental-rv64-legal-i32 | FileCheck %s --check-prefix=RV64ZBA
+; RUN: llc < %s -mtriple=riscv64 -mattr=+m,+zicond -verify-machineinstrs \
+; RUN: -riscv-experimental-rv64-legal-i32 | FileCheck %s --check-prefix=RV64ZICOND
;
; Get the actual value of the overflow bit.
@@ -14,6 +18,24 @@ define zeroext i1 @saddo1.i32(i32 signext %v1, i32 signext %v2, ptr %res) {
; RV64-NEXT: snez a0, a3
; RV64-NEXT: sw a1, 0(a2)
; RV64-NEXT: ret
+;
+; RV64ZBA-LABEL: saddo1.i32:
+; RV64ZBA: # %bb.0: # %entry
+; RV64ZBA-NEXT: addw a3, a0, a1
+; RV64ZBA-NEXT: add a1, a0, a1
+; RV64ZBA-NEXT: xor a3, a1, a3
+; RV64ZBA-NEXT: snez a0, a3
+; RV64ZBA-NEXT: sw a1, 0(a2)
+; RV64ZBA-NEXT: ret
+;
+; RV64ZICOND-LABEL: saddo1.i32:
+; RV64ZICOND: # %bb.0: # %entry
+; RV64ZICOND-NEXT: addw a3, a0, a1
+; RV64ZICOND-NEXT: add a1, a0, a1
+; RV64ZICOND-NEXT: xor a3, a1, a3
+; RV64ZICOND-NEXT: snez a0, a3
+; RV64ZICOND-NEXT: sw a1, 0(a2)
+; RV64ZICOND-NEXT: ret
entry:
%t = call {i32, i1} @llvm.sadd.with.overflow.i32(i32 %v1, i32 %v2)
%val = extractvalue {i32, i1} %t, 0
@@ -30,6 +52,20 @@ define zeroext i1 @saddo2.i32(i32 signext %v1, ptr %res) {
; RV64-NEXT: slt a0, a2, a0
; RV64-NEXT: sw a2, 0(a1)
; RV64-NEXT: ret
+;
+; RV64ZBA-LABEL: saddo2.i32:
+; RV64ZBA: # %bb.0: # %entry
+; RV64ZBA-NEXT: addiw a2, a0, 4
+; RV64ZBA-NEXT: slt a0, a2, a0
+; RV64ZBA-NEXT: sw a2, 0(a1)
+; RV64ZBA-NEXT: ret
+;
+; RV64ZICOND-LABEL: saddo2.i32:
+; RV64ZICOND: # %bb.0: # %entry
+; RV64ZICOND-NEXT: addiw a2, a0, 4
+; RV64ZICOND-NEXT: slt a0, a2, a0
+; RV64ZICOND-NEXT: sw a2, 0(a1)
+; RV64ZICOND-NEXT: ret
entry:
%t = call {i32, i1} @llvm.sadd.with.overflow.i32(i32 %v1, i32 4)
%val = extractvalue {i32, i1} %t, 0
@@ -47,6 +83,22 @@ define zeroext i1 @saddo3.i32(i32 signext %v1, ptr %res) {
; RV64-NEXT: xori a0, a0, 1
; RV64-NEXT: sw a2, 0(a1)
; RV64-NEXT: ret
+;
+; RV64ZBA-LABEL: saddo3.i32:
+; RV64ZBA: # %bb.0: # %entry
+; RV64ZBA-NEXT: addiw a2, a0, -4
+; RV64ZBA-NEXT: slt a0, a2, a0
+; RV64ZBA-NEXT: xori a0, a0, 1
+; RV64ZBA-NEXT: sw a2, 0(a1)
+; RV64ZBA-NEXT: ret
+;
+; RV64ZICOND-LABEL: saddo3.i32:
+; RV64ZICOND: # %bb.0: # %entry
+; RV64ZICOND-NEXT: addiw a2, a0, -4
+; RV64ZICOND-NEXT: slt a0, a2, a0
+; RV64ZICOND-NEXT: xori a0, a0, 1
+; RV64ZICOND-NEXT: sw a2, 0(a1)
+; RV64ZICOND-NEXT: ret
entry:
%t = call {i32, i1} @llvm.sadd.with.overflow.i32(i32 %v1, i32 -4)
%val = extractvalue {i32, i1} %t, 0
@@ -65,6 +117,24 @@ define zeroext i1 @saddo4.i32(i32 signext %v1, ptr %res) {
; RV64-NEXT: slt a0, a2, a0
; RV64-NEXT: sw a2, 0(a1)
; RV64-NEXT: ret
+;
+; RV64ZBA-LABEL: saddo4.i32:
+; RV64ZBA: # %bb.0: # %entry
+; RV64ZBA-NEXT: lui a2, 4096
+; RV64ZBA-NEXT: addi a2, a2, -1
+; RV64ZBA-NEXT: addw a2, a0, a2
+; RV64ZBA-NEXT: slt a0, a2, a0
+; RV64ZBA-NEXT: sw a2, 0(a1)
+; RV64ZBA-NEXT: ret
+;
+; RV64ZICOND-LABEL: saddo4.i32:
+; RV64ZICOND: # %bb.0: # %entry
+; RV64ZICOND-NEXT: lui a2, 4096
+; RV64ZICOND-NEXT: addi a2, a2, -1
+; RV64ZICOND-NEXT: addw a2, a0, a2
+; RV64ZICOND-NEXT: slt a0, a2, a0
+; RV64ZICOND-NEXT: sw a2, 0(a1)
+; RV64ZICOND-NEXT: ret
entry:
%t = call {i32, i1} @llvm.sadd.with.overflow.i32(i32 %v1, i32 16777215)
%val = extractvalue {i32, i1} %t, 0
@@ -82,6 +152,24 @@ define zeroext i1 @saddo1.i64(i64 %v1, i64 %v2, ptr %res) {
; RV64-NEXT: xor a0, a1, a0
; RV64-NEXT: sd a3, 0(a2)
; RV64-NEXT: ret
+;
+; RV64ZBA-LABEL: saddo1.i64:
+; RV64ZBA: # %bb.0: # %entry
+; RV64ZBA-NEXT: add a3, a0, a1
+; RV64ZBA-NEXT: slt a0, a3, a0
+; RV64ZBA-NEXT: slti a1, a1, 0
+; RV64ZBA-NEXT: xor a0, a1, a0
+; RV64ZBA-NEXT: sd a3, 0(a2)
+; RV64ZBA-NEXT: ret
+;
+; RV64ZICOND-LABEL: saddo1.i64:
+; RV64ZICOND: # %bb.0: # %entry
+; RV64ZICOND-NEXT: add a3, a0, a1
+; RV64ZICOND-NEXT: slt a0, a3, a0
+; RV64ZICOND-NEXT: slti a1, a1, 0
+; RV64ZICOND-NEXT: xor a0, a1, a0
+; RV64ZICOND-NEXT: sd a3, 0(a2)
+; RV64ZICOND-NEXT: ret
entry:
%t = call {i64, i1} @llvm.sadd.with.overflow.i64(i64 %v1, i64 %v2)
%val = extractvalue {i64, i1} %t, 0
@@ -97,6 +185,20 @@ define zeroext i1 @saddo2.i64(i64 %v1, ptr %res) {
; RV64-NEXT: slt a0, a2, a0
; RV64-NEXT: sd a2, 0(a1)
; RV64-NEXT: ret
+;
+; RV64ZBA-LABEL: saddo2.i64:
+; RV64ZBA: # %bb.0: # %entry
+; RV64ZBA-NEXT: addi a2, a0, 4
+; RV64ZBA-NEXT: slt a0, a2, a0
+; RV64ZBA-NEXT: sd a2, 0(a1)
+; RV64ZBA-NEXT: ret
+;
+; RV64ZICOND-LABEL: saddo2.i64:
+; RV64ZICOND: # %bb.0: # %entry
+; RV64ZICOND-NEXT: addi a2, a0, 4
+; RV64ZICOND-NEXT: slt a0, a2, a0
+; RV64ZICOND-NEXT: sd a2, 0(a1)
+; RV64ZICOND-NEXT: ret
entry:
%t = call {i64, i1} @llvm.sadd.with.overflow.i64(i64 %v1, i64 4)
%val = extractvalue {i64, i1} %t, 0
@@ -113,6 +215,22 @@ define zeroext i1 @saddo3.i64(i64 %v1, ptr %res) {
; RV64-NEXT: xori a0, a0, 1
; RV64-NEXT: sd a2, 0(a1)
; RV64-NEXT: ret
+;
+; RV64ZBA-LABEL: saddo3.i64:
+; RV64ZBA: # %bb.0: # %entry
+; RV64ZBA-NEXT: addi a2, a0, -4
+; RV64ZBA-NEXT: slt a0, a2, a0
+; RV64ZBA-NEXT: xori a0, a0, 1
+; RV64ZBA-NEXT: sd a2, 0(a1)
+; RV64ZBA-NEXT: ret
+;
+; RV64ZICOND-LABEL: saddo3.i64:
+; RV64ZICOND: # %bb.0: # %entry
+; RV64ZICOND-NEXT: addi a2, a0, -4
+; RV64ZICOND-NEXT: slt a0, a2, a0
+; RV64ZICOND-NEXT: xori a0, a0, 1
+; RV64ZICOND-NEXT: sd a2, 0(a1)
+; RV64ZICOND-NEXT: ret
entry:
%t = call {i64, i1} @llvm.sadd.with.overflow.i64(i64 %v1, i64 -4)
%val = extractvalue {i64, i1} %t, 0
@@ -128,6 +246,20 @@ define zeroext i1 @uaddo.i32(i32 signext %v1, i32 signext %v2, ptr %res) {
; RV64-NEXT: sltu a0, a1, a0
; RV64-NEXT: sw a1, 0(a2)
; RV64-NEXT: ret
+;
+; RV64ZBA-LABEL: uaddo.i32:
+; RV64ZBA: # %bb.0: # %entry
+; RV64ZBA-NEXT: addw a1, a0, a1
+; RV64ZBA-NEXT: sltu a0, a1, a0
+; RV64ZBA-NEXT: sw a1, 0(a2)
+; RV64ZBA-NEXT: ret
+;
+; RV64ZICOND-LABEL: uaddo.i32:
+; RV64ZICOND: # %bb.0: # %entry
+; RV64ZICOND-NEXT: addw a1, a0, a1
+; RV64ZICOND-NEXT: sltu a0, a1, a0
+; RV64ZICOND-NEXT: sw a1, 0(a2)
+; RV64ZICOND-NEXT: ret
entry:
%t = call {i32, i1} @llvm.uadd.with.overflow.i32(i32 %v1, i32 %v2)
%val = extractvalue {i32, i1} %t, 0
@@ -143,6 +275,20 @@ define zeroext i1 @uaddo.i32.constant(i32 signext %v1, ptr %res) {
; RV64-NEXT: sltu a0, a2, a0
; RV64-NEXT: sw a2, 0(a1)
; RV64-NEXT: ret
+;
+; RV64ZBA-LABEL: uaddo.i32.constant:
+; RV64ZBA: # %bb.0: # %entry
+; RV64ZBA-NEXT: addiw a2, a0, -2
+; RV64ZBA-NEXT: sltu a0, a2, a0
+; RV64ZBA-NEXT: sw a2, 0(a1)
+; RV64ZBA-NEXT: ret
+;
+; RV64ZICOND-LABEL: uaddo.i32.constant:
+; RV64ZICOND: # %bb.0: # %entry
+; RV64ZICOND-NEXT: addiw a2, a0, -2
+; RV64ZICOND-NEXT: sltu a0, a2, a0
+; RV64ZICOND-NEXT: sw a2, 0(a1)
+; RV64ZICOND-NEXT: ret
entry:
%t = call {i32, i1} @llvm.uadd.with.overflow.i32(i32 %v1, i32 -2)
%val = extractvalue {i32, i1} %t, 0
@@ -158,6 +304,20 @@ define zeroext i1 @uaddo.i32.constant_one(i32 signext %v1, ptr %res) {
; RV64-NEXT: seqz a0, a2
; RV64-NEXT: sw a2, 0(a1)
; RV64-NEXT: ret
+;
+; RV64ZBA-LABEL: uaddo.i32.constant_one:
+; RV64ZBA: # %bb.0: # %entry
+; RV64ZBA-NEXT: addiw a2, a0, 1
+; RV64ZBA-NEXT: seqz a0, a2
+; RV64ZBA-NEXT: sw a2, 0(a1)
+; RV64ZBA-NEXT: ret
+;
+; RV64ZICOND-LABEL: uaddo.i32.constant_one:
+; RV64ZICOND: # %bb.0: # %entry
+; RV64ZICOND-NEXT: addiw a2, a0, 1
+; RV64ZICOND-NEXT: seqz a0, a2
+; RV64ZICOND-NEXT: sw a2, 0(a1)
+; RV64ZICOND-NEXT: ret
entry:
%t = call {i32, i1} @llvm.uadd.with.overflow.i32(i32 %v1, i32 1)
%val = extractvalue {i32, i1} %t, 0
@@ -173,6 +333,20 @@ define zeroext i1 @uaddo.i64(i64 %v1, i64 %v2, ptr %res) {
; RV64-NEXT: sltu a0, a1, a0
; RV64-NEXT: sd a1, 0(a2)
; RV64-NEXT: ret
+;
+; RV64ZBA-LABEL: uaddo.i64:
+; RV64ZBA: # %bb.0: # %entry
+; RV64ZBA-NEXT: add a1, a0, a1
+; RV64ZBA-NEXT: sltu a0, a1, a0
+; RV64ZBA-NEXT: sd a1, 0(a2)
+; RV64ZBA-NEXT: ret
+;
+; RV64ZICOND-LABEL: uaddo.i64:
+; RV64ZICOND: # %bb.0: # %entry
+; RV64ZICOND-NEXT: add a1, a0, a1
+; RV64ZICOND-NEXT: sltu a0, a1, a0
+; RV64ZICOND-NEXT: sd a1, 0(a2)
+; RV64ZICOND-NEXT: ret
entry:
%t = call {i64, i1} @llvm.uadd.with.overflow.i64(i64 %v1, i64 %v2)
%val = extractvalue {i64, i1} %t, 0
@@ -188,6 +362,20 @@ define zeroext i1 @uaddo.i64.constant_one(i64 %v1, ptr %res) {
; RV64-NEXT: seqz a0, a2
; RV64-NEXT: sd a2, 0(a1)
; RV64-NEXT: ret
+;
+; RV64ZBA-LABEL: uaddo.i64.constant_one:
+; RV64ZBA: # %bb.0: # %entry
+; RV64ZBA-NEXT: addi a2, a0, 1
+; RV64ZBA-NEXT: seqz a0, a2
+; RV64ZBA-NEXT: sd a2, 0(a1)
+; RV64ZBA-NEXT: ret
+;
+; RV64ZICOND-LABEL: uaddo.i64.constant_one:
+; RV64ZICOND: # %bb.0: # %entry
+; RV64ZICOND-NEXT: addi a2, a0, 1
+; RV64ZICOND-NEXT: seqz a0, a2
+; RV64ZICOND-NEXT: sd a2, 0(a1)
+; RV64ZICOND-NEXT: ret
entry:
%t = call {i64, i1} @llvm.uadd.with.overflow.i64(i64 %v1, i64 1)
%val = extractvalue {i64, i1} %t, 0
@@ -205,6 +393,24 @@ define zeroext i1 @ssubo1.i32(i32 signext %v1, i32 signext %v2, ptr %res) {
; RV64-NEXT: snez a0, a3
; RV64-NEXT: sw a1, 0(a2)
; RV64-NEXT: ret
+;
+; RV64ZBA-LABEL: ssubo1.i32:
+; RV64ZBA: # %bb.0: # %entry
+; RV64ZBA-NEXT: subw a3, a0, a1
+; RV64ZBA-NEXT: sub a1, a0, a1
+; RV64ZBA-NEXT: xor a3, a1, a3
+; RV64ZBA-NEXT: snez a0, a3
+; RV64ZBA-NEXT: sw a1, 0(a2)
+; RV64ZBA-NEXT: ret
+;
+; RV64ZICOND-LABEL: ssubo1.i32:
+; RV64ZICOND: # %bb.0: # %entry
+; RV64ZICOND-NEXT: subw a3, a0, a1
+; RV64ZICOND-NEXT: sub a1, a0, a1
+; RV64ZICOND-NEXT: xor a3, a1, a3
+; RV64ZICOND-NEXT: snez a0, a3
+; RV64ZICOND-NEXT: sw a1, 0(a2)
+; RV64ZICOND-NEXT: ret
entry:
%t = call {i32, i1} @llvm.ssub.with.overflow.i32(i32 %v1, i32 %v2)
%val = extractvalue {i32, i1} %t, 0
@@ -220,6 +426,20 @@ define zeroext i1 @ssubo2.i32(i32 signext %v1, ptr %res) {
; RV64-NEXT: slt a0, a2, a0
; RV64-NEXT: sw a2, 0(a1)
; RV64-NEXT: ret
+;
+; RV64ZBA-LABEL: ssubo2.i32:
+; RV64ZBA: # %bb.0: # %entry
+; RV64ZBA-NEXT: addiw a2, a0, 4
+; RV64ZBA-NEXT: slt a0, a2, a0
+; RV64ZBA-NEXT: sw a2, 0(a1)
+; RV64ZBA-NEXT: ret
+;
+; RV64ZICOND-LABEL: ssubo2.i32:
+; RV64ZICOND: # %bb.0: # %entry
+; RV64ZICOND-NEXT: addiw a2, a0, 4
+; RV64ZICOND-NEXT: slt a0, a2, a0
+; RV64ZICOND-NEXT: sw a2, 0(a1)
+; RV64ZICOND-NEXT: ret
entry:
%t = call {i32, i1} @llvm.ssub.with.overflow.i32(i32 %v1, i32 -4)
%val = extractvalue {i32, i1} %t, 0
@@ -237,6 +457,24 @@ define zeroext i1 @ssubo.i64(i64 %v1, i64 %v2, ptr %res) {
; RV64-NEXT: xor a0, a3, a0
; RV64-NEXT: sd a1, 0(a2)
; RV64-NEXT: ret
+;
+; RV64ZBA-LABEL: ssubo.i64:
+; RV64ZBA: # %bb.0: # %entry
+; RV64ZBA-NEXT: sgtz a3, a1
+; RV64ZBA-NEXT: sub a1, a0, a1
+; RV64ZBA-NEXT: slt a0, a1, a0
+; RV64ZBA-NEXT: xor a0, a3, a0
+; RV64ZBA-NEXT: sd a1, 0(a2)
+; RV64ZBA-NEXT: ret
+;
+; RV64ZICOND-LABEL: ssubo.i64:
+; RV64ZICOND: # %bb.0: # %entry
+; RV64ZICOND-NEXT: sgtz a3, a1
+; RV64ZICOND-NEXT: sub a1, a0, a1
+; RV64ZICOND-NEXT: slt a0, a1, a0
+; RV64ZICOND-NEXT: xor a0, a3, a0
+; RV64ZICOND-NEXT: sd a1, 0(a2)
+; RV64ZICOND-NEXT: ret
entry:
%t = call {i64, i1} @llvm.ssub.with.overflow.i64(i64 %v1, i64 %v2)
%val = extractvalue {i64, i1} %t, 0
@@ -252,6 +490,20 @@ define zeroext i1 @usubo.i32(i32 signext %v1, i32 signext %v2, ptr %res) {
; RV64-NEXT: sltu a0, a0, a1
; RV64-NEXT: sw a1, 0(a2)
; RV64-NEXT: ret
+;
+; RV64ZBA-LABEL: usubo.i32:
+; RV64ZBA: # %bb.0: # %entry
+; RV64ZBA-NEXT: subw a1, a0, a1
+; RV64ZBA-NEXT: sltu a0, a0, a1
+; RV64ZBA-NEXT: sw a1, 0(a2)
+; RV64ZBA-NEXT: ret
+;
+; RV64ZICOND-LABEL: usubo.i32:
+; RV64ZICOND: # %bb.0: # %entry
+; RV64ZICOND-NEXT: subw a1, a0, a1
+; RV64ZICOND-NEXT: sltu a0, a0, a1
+; RV64ZICOND-NEXT: sw a1, 0(a2)
+; RV64ZICOND-NEXT: ret
entry:
%t = call {i32, i1} @llvm.usub.with.overflow.i32(i32 %v1, i32 %v2)
%val = extractvalue {i32, i1} %t, 0
@@ -267,6 +519,20 @@ define zeroext i1 @usubo.i32.constant.rhs(i32 signext %v1, ptr %res) {
; RV64-NEXT: sltu a0, a0, a2
; RV64-NEXT: sw a2, 0(a1)
; RV64-NEXT: ret
+;
+; RV64ZBA-LABEL: usubo.i32.constant.rhs:
+; RV64ZBA: # %bb.0: # %entry
+; RV64ZBA-NEXT: addiw a2, a0, 2
+; RV64ZBA-NEXT: sltu a0, a0, a2
+; RV64ZBA-NEXT: sw a2, 0(a1)
+; RV64ZBA-NEXT: ret
+;
+; RV64ZICOND-LABEL: usubo.i32.constant.rhs:
+; RV64ZICOND: # %bb.0: # %entry
+; RV64ZICOND-NEXT: addiw a2, a0, 2
+; RV64ZICOND-NEXT: sltu a0, a0, a2
+; RV64ZICOND-NEXT: sw a2, 0(a1)
+; RV64ZICOND-NEXT: ret
entry:
%t = call {i32, i1} @llvm.usub.with.overflow.i32(i32 %v1, i32 -2)
%val = extractvalue {i32, i1} %t, 0
@@ -284,6 +550,24 @@ define zeroext i1 @usubo.i32.constant.lhs(i32 signext %v1, ptr %res) {
; RV64-NEXT: seqz a0, a0
; RV64-NEXT: sw a2, 0(a1)
; RV64-NEXT: ret
+;
+; RV64ZBA-LABEL: usubo.i32.constant.lhs:
+; RV64ZBA: # %bb.0: # %entry
+; RV64ZBA-NEXT: li a2, -2
+; RV64ZBA-NEXT: subw a2, a2, a0
+; RV64ZBA-NEXT: addi a0, a2, 1
+; RV64ZBA-NEXT: seqz a0, a0
+; RV64ZBA-NEXT: sw a2, 0(a1)
+; RV64ZBA-NEXT: ret
+;
+; RV64ZICOND-LABEL: usubo.i32.constant.lhs:
+; RV64ZICOND: # %bb.0: # %entry
+; RV64ZICOND-NEXT: li a2, -2
+; RV64ZICOND-NEXT: subw a2, a2, a0
+; RV64ZICOND-NEXT: addi a0, a2, 1
+; RV64ZICOND-NEXT: seqz a0, a0
+; RV64ZICOND-NEXT: sw a2, 0(a1)
+; RV64ZICOND-NEXT: ret
entry:
%t = call {i32, i1} @llvm.usub.with.overflow.i32(i32 -2, i32 %v1)
%val = extractvalue {i32, i1} %t, 0
@@ -299,6 +583,20 @@ define zeroext i1 @usubo.i64(i64 %v1, i64 %v2, ptr %res) {
; RV64-NEXT: sltu a0, a0, a1
; RV64-NEXT: sd a1, 0(a2)
; RV64-NEXT: ret
+;
+; RV64ZBA-LABEL: usubo.i64:
+; RV64ZBA: # %bb.0: # %entry
+; RV64ZBA-NEXT: sub a1, a0, a1
+; RV64ZBA-NEXT: sltu a0, a0, a1
+; RV64ZBA-NEXT: sd a1, 0(a2)
+; RV64ZBA-NEXT: ret
+;
+; RV64ZICOND-LABEL: usubo.i64:
+; RV64ZICOND: # %bb.0: # %entry
+; RV64ZICOND-NEXT: sub a1, a0, a1
+; RV64ZICOND-NEXT: sltu a0, a0, a1
+; RV64ZICOND-NEXT: sd a1, 0(a2)
+; RV64ZICOND-NEXT: ret
entry:
%t = call {i64, i1} @llvm.usub.with.overflow.i64(i64 %v1, i64 %v2)
%val = extractvalue {i64, i1} %t, 0
@@ -316,6 +614,24 @@ define zeroext i1 @smulo.i32(i32 signext %v1, i32 signext %v2, ptr %res) {
; RV64-NEXT: snez a0, a3
; RV64-NEXT: sw a1, 0(a2)
; RV64-NEXT: ret
+;
+; RV64ZBA-LABEL: smulo.i32:
+; RV64ZBA: # %bb.0: # %entry
+; RV64ZBA-NEXT: mulw a3, a0, a1
+; RV64ZBA-NEXT: mul a1, a0, a1
+; RV64ZBA-NEXT: xor a3, a1, a3
+; RV64ZBA-NEXT: snez a0, a3
+; RV64ZBA-NEXT: sw a1, 0(a2)
+; RV64ZBA-NEXT: ret
+;
+; RV64ZICOND-LABEL: smulo.i32:
+; RV64ZICOND: # %bb.0: # %entry
+; RV64ZICOND-NEXT: mulw a3, a0, a1
+; RV64ZICOND-NEXT: mul a1, a0, a1
+; RV64ZICOND-NEXT: xor a3, a1, a3
+; RV64ZICOND-NEXT: snez a0, a3
+; RV64ZICOND-NEXT: sw a1, 0(a2)
+; RV64ZICOND-NEXT: ret
entry:
%t = call {i32, i1} @llvm.smul.with.overflow.i32(i32 %v1, i32 %v2)
%val = extractvalue {i32, i1} %t, 0
@@ -334,6 +650,26 @@ define zeroext i1 @smulo2.i32(i32 signext %v1, ptr %res) {
; RV64-NEXT: snez a0, a3
; RV64-NEXT: sw a2, 0(a1)
; RV64-NEXT: ret
+;
+; RV64ZBA-LABEL: smulo2.i32:
+; RV64ZBA: # %bb.0: # %entry
+; RV64ZBA-NEXT: sh1add a2, a0, a0
+; RV64ZBA-NEXT: sh2add a2, a2, a0
+; RV64ZBA-NEXT: sext.w a0, a2
+; RV64ZBA-NEXT: xor a0, a2, a0
+; RV64ZBA-NEXT: snez a0, a0
+; RV64ZBA-NEXT: sw a2, 0(a1)
+; RV64ZBA-NEXT: ret
+;
+; RV64ZICOND-LABEL: smulo2.i32:
+; RV64ZICOND: # %bb.0: # %entry
+; RV64ZICOND-NEXT: li a2, 13
+; RV64ZICOND-NEXT: mulw a3, a0, a2
+; RV64ZICOND-NEXT: mul a2, a0, a2
+; RV64ZICOND-NEXT: xor a3, a2, a3
+; RV64ZICOND-NEXT: snez a0, a3
+; RV64ZICOND-NEXT: sw a2, 0(a1)
+; RV64ZICOND-NEXT: ret
entry:
%t = call {i32, i1} @llvm.smul.with.overflow.i32(i32 %v1, i32 13)
%val = extractvalue {i32, i1} %t, 0
@@ -352,6 +688,26 @@ define zeroext i1 @smulo.i64(i64 %v1, i64 %v2, ptr %res) {
; RV64-NEXT: snez a0, a0
; RV64-NEXT: sd a1, 0(a2)
; RV64-NEXT: ret
+;
+; RV64ZBA-LABEL: smulo.i64:
+; RV64ZBA: # %bb.0: # %entry
+; RV64ZBA-NEXT: mulh a3, a0, a1
+; RV64ZBA-NEXT: mul a1, a0, a1
+; RV64ZBA-NEXT: srai a0, a1, 63
+; RV64ZBA-NEXT: xor a0, a3, a0
+; RV64ZBA-NEXT: snez a0, a0
+; RV64ZBA-NEXT: sd a1, 0(a2)
+; RV64ZBA-NEXT: ret
+;
+; RV64ZICOND-LABEL: smulo.i64:
+; RV64ZICOND: # %bb.0: # %entry
+; RV64ZICOND-NEXT: mulh a3, a0, a1
+; RV64ZICOND-NEXT: mul a1, a0, a1
+; RV64ZICOND-NEXT: srai a0, a1, 63
+; RV64ZICOND-NEXT: xor a0, a3, a0
+; RV64ZICOND-NEXT: snez a0, a0
+; RV64ZICOND-NEXT: sd a1, 0(a2)
+; RV64ZICOND-NEXT: ret
entry:
%t = call {i64, i1} @llvm.smul.with.overflow.i64(i64 %v1, i64 %v2)
%val = extractvalue {i64, i1} %t, 0
@@ -371,6 +727,28 @@ define zeroext i1 @smulo2.i64(i64 %v1, ptr %res) {
; RV64-NEXT: snez a0, a0
; RV64-NEXT: sd a2, 0(a1)
; RV64-NEXT: ret
+;
+; RV64ZBA-LABEL: smulo2.i64:
+; RV64ZBA: # %bb.0: # %entry
+; RV64ZBA-NEXT: li a2, 13
+; RV64ZBA-NEXT: mulh a3, a0, a2
+; RV64ZBA-NEXT: mul a2, a0, a2
+; RV64ZBA-NEXT: srai a0, a2, 63
+; RV64ZBA-NEXT: xor a0, a3, a0
+; RV64ZBA-NEXT: snez a0, a0
+; RV64ZBA-NEXT: sd a2, 0(a1)
+; RV64ZBA-NEXT: ret
+;
+; RV64ZICOND-LABEL: smulo2.i64:
+; RV64ZICOND: # %bb.0: # %entry
+; RV64ZICOND-NEXT: li a2, 13
+; RV64ZICOND-NEXT: mulh a3, a0, a2
+; RV64ZICOND-NEXT: mul a2, a0, a2
+; RV64ZICOND-NEXT: srai a0, a2, 63
+; RV64ZICOND-NEXT: xor a0, a3, a0
+; RV64ZICOND-NEXT: snez a0, a0
+; RV64ZICOND-NEXT: sd a2, 0(a1)
+; RV64ZICOND-NEXT: ret
entry:
%t = call {i64, i1} @llvm.smul.with.overflow.i64(i64 %v1, i64 13)
%val = extractvalue {i64, i1} %t, 0
@@ -389,6 +767,26 @@ define zeroext i1 @umulo.i32(i32 signext %v1, i32 signext %v2, ptr %res) {
; RV64-NEXT: snez a0, a0
; RV64-NEXT: sw a1, 0(a2)
; RV64-NEXT: ret
+;
+; RV64ZBA-LABEL: umulo.i32:
+; RV64ZBA: # %bb.0: # %entry
+; RV64ZBA-NEXT: zext.w a1, a1
+; RV64ZBA-NEXT: zext.w a0, a0
+; RV64ZBA-NEXT: mul a1, a0, a1
+; RV64ZBA-NEXT: srai a0, a1, 32
+; RV64ZBA-NEXT: snez a0, a0
+; RV64ZBA-NEXT: sw a1, 0(a2)
+; RV64ZBA-NEXT: ret
+;
+; RV64ZICOND-LABEL: umulo.i32:
+; RV64ZICOND: # %bb.0: # %entry
+; RV64ZICOND-NEXT: slli a1, a1, 32
+; RV64ZICOND-NEXT: slli a0, a0, 32
+; RV64ZICOND-NEXT: mulhu a1, a0, a1
+; RV64ZICOND-NEXT: srai a0, a1, 32
+; RV64ZICOND-NEXT: snez a0, a0
+; RV64ZICOND-NEXT: sw a1, 0(a2)
+; RV64ZICOND-NEXT: ret
entry:
%t = call {i32, i1} @llvm.umul.with.overflow.i32(i32 %v1, i32 %v2)
%val = extractvalue {i32, i1} %t, 0
@@ -408,6 +806,27 @@ define zeroext i1 @umulo2.i32(i32 signext %v1, ptr %res) {
; RV64-NEXT: snez a0, a0
; RV64-NEXT: sw a2, 0(a1)
; RV64-NEXT: ret
+;
+; RV64ZBA-LABEL: umulo2.i32:
+; RV64ZBA: # %bb.0: # %entry
+; RV64ZBA-NEXT: zext.w a0, a0
+; RV64ZBA-NEXT: sh1add a2, a0, a0
+; RV64ZBA-NEXT: sh2add a2, a2, a0
+; RV64ZBA-NEXT: srli a0, a2, 32
+; RV64ZBA-NEXT: snez a0, a0
+; RV64ZBA-NEXT: sw a2, 0(a1)
+; RV64ZBA-NEXT: ret
+;
+; RV64ZICOND-LABEL: umulo2.i32:
+; RV64ZICOND: # %bb.0: # %entry
+; RV64ZICOND-NEXT: li a2, 13
+; RV64ZICOND-NEXT: slli a2, a2, 32
+; RV64ZICOND-NEXT: slli a0, a0, 32
+; RV64ZICOND-NEXT: mulhu a2, a0, a2
+; RV64ZICOND-NEXT: srli a0, a2, 32
+; RV64ZICOND-NEXT: snez a0, a0
+; RV64ZICOND-NEXT: sw a2, 0(a1)
+; RV64ZICOND-NEXT: ret
entry:
%t = call {i32, i1} @llvm.umul.with.overflow.i32(i32 %v1, i32 13)
%val = extractvalue {i32, i1} %t, 0
@@ -428,6 +847,28 @@ define signext i32 @umulo3.i32(i32 signext %0, i32 signext %1, ptr %2) {
; RV64-NEXT: sext.w a0, a0
; RV64-NEXT: sw a1, 0(a2)
; RV64-NEXT: ret
+;
+; RV64ZBA-LABEL: umulo3.i32:
+; RV64ZBA: # %bb.0:
+; RV64ZBA-NEXT: zext.w a1, a1
+; RV64ZBA-NEXT: zext.w a0, a0
+; RV64ZBA-NEXT: mul a3, a0, a1
+; RV64ZBA-NEXT: srai a3, a3, 32
+; RV64ZBA-NEXT: snez a3, a3
+; RV64ZBA-NEXT: mulw a0, a0, a1
+; RV64ZBA-NEXT: sw a3, 0(a2)
+; RV64ZBA-NEXT: ret
+;
+; RV64ZICOND-LABEL: umulo3.i32:
+; RV64ZICOND: # %bb.0:
+; RV64ZICOND-NEXT: slli a1, a1, 32
+; RV64ZICOND-NEXT: slli a0, a0, 32
+; RV64ZICOND-NEXT: mulhu a0, a0, a1
+; RV64ZICOND-NEXT: srai a1, a0, 32
+; RV64ZICOND-NEXT: snez a1, a1
+; RV64ZICOND-NEXT: sext.w a0, a0
+; RV64ZICOND-NEXT: sw a1, 0(a2)
+; RV64ZICOND-NEXT: ret
%4 = tail call { i32, i1 } @llvm.umul.with.overflow.i32(i32 %0, i32 %1)
%5 = extractvalue { i32, i1 } %4, 1
%6 = extractvalue { i32, i1 } %4, 0
@@ -445,6 +886,24 @@ define zeroext i1 @umulo.i64(i64 %v1, i64 %v2, ptr %res) {
; RV64-NEXT: sd a0, 0(a2)
; RV64-NEXT: mv a0, a3
; RV64-NEXT: ret
+;
+; RV64ZBA-LABEL: umulo.i64:
+; RV64ZBA: # %bb.0: # %entry
+; RV64ZBA-NEXT: mulhu a3, a0, a1
+; RV64ZBA-NEXT: snez a3, a3
+; RV64ZBA-NEXT: mul a0, a0, a1
+; RV64ZBA-NEXT: sd a0, 0(a2)
+; RV64ZBA-NEXT: mv a0, a3
+; RV64ZBA-NEXT: ret
+;
+; RV64ZICOND-LABEL: umulo.i64:
+; RV64ZICOND: # %bb.0: # %entry
+; RV64ZICOND-NEXT: mulhu a3, a0, a1
+; RV64ZICOND-NEXT: snez a3, a3
+; RV64ZICOND-NEXT: mul a0, a0, a1
+; RV64ZICOND-NEXT: sd a0, 0(a2)
+; RV64ZICOND-NEXT: mv a0, a3
+; RV64ZICOND-NEXT: ret
entry:
%t = call {i64, i1} @llvm.umul.with.overflow.i64(i64 %v1, i64 %v2)
%val = extractvalue {i64, i1} %t, 0
@@ -463,6 +922,26 @@ define zeroext i1 @umulo2.i64(i64 %v1, ptr %res) {
; RV64-NEXT: sd a0, 0(a1)
; RV64-NEXT: mv a0, a2
; RV64-NEXT: ret
+;
+; RV64ZBA-LABEL: umulo2.i64:
+; RV64ZBA: # %bb.0: # %entry
+; RV64ZBA-NEXT: li a3, 13
+; RV64ZBA-NEXT: mulhu a2, a0, a3
+; RV64ZBA-NEXT: snez a2, a2
+; RV64ZBA-NEXT: mul a0, a0, a3
+; RV64ZBA-NEXT: sd a0, 0(a1)
+; RV64ZBA-NEXT: mv a0, a2
+; RV64ZBA-NEXT: ret
+;
+; RV64ZICOND-LABEL: umulo2.i64:
+; RV64ZICOND: # %bb.0: # %entry
+; RV64ZICOND-NEXT: li a3, 13
+; RV64ZICOND-NEXT: mulhu a2, a0, a3
+; RV64ZICOND-NEXT: snez a2, a2
+; RV64ZICOND-NEXT: mul a0, a0, a3
+; RV64ZICOND-NEXT: sd a0, 0(a1)
+; RV64ZICOND-NEXT: mv a0, a2
+; RV64ZICOND-NEXT: ret
entry:
%t = call {i64, i1} @llvm.umul.with.overflow.i64(i64 %v1, i64 13)
%val = extractvalue {i64, i1} %t, 0
@@ -485,6 +964,26 @@ define i32 @saddo.select.i32(i32 signext %v1, i32 signext %v2) {
; RV64-NEXT: mv a0, a1
; RV64-NEXT: .LBB28_2: # %entry
; RV64-NEXT: ret
+;
+; RV64ZBA-LABEL: saddo.select.i32:
+; RV64ZBA: # %bb.0: # %entry
+; RV64ZBA-NEXT: addw a2, a0, a1
+; RV64ZBA-NEXT: add a3, a0, a1
+; RV64ZBA-NEXT: bne a3, a2, .LBB28_2
+; RV64ZBA-NEXT: # %bb.1: # %entry
+; RV64ZBA-NEXT: mv a0, a1
+; RV64ZBA-NEXT: .LBB28_2: # %entry
+; RV64ZBA-NEXT: ret
+;
+; RV64ZICOND-LABEL: saddo.select.i32:
+; RV64ZICOND: # %bb.0: # %entry
+; RV64ZICOND-NEXT: addw a2, a0, a1
+; RV64ZICOND-NEXT: add a3, a0, a1
+; RV64ZICOND-NEXT: xor a2, a3, a2
+; RV64ZICOND-NEXT: czero.nez a1, a1, a2
+; RV64ZICOND-NEXT: czero.eqz a0, a0, a2
+; RV64ZICOND-NEXT: or a0, a0, a1
+; RV64ZICOND-NEXT: ret
entry:
%t = call {i32, i1} @llvm.sadd.with.overflow.i32(i32 %v1, i32 %v2)
%obit = extractvalue {i32, i1} %t, 1
@@ -501,6 +1000,24 @@ define i1 @saddo.not.i32(i32 signext %v1, i32 signext %v2) {
; RV64-NEXT: snez a0, a0
; RV64-NEXT: xori a0, a0, 1
; RV64-NEXT: ret
+;
+; RV64ZBA-LABEL: saddo.not.i32:
+; RV64ZBA: # %bb.0: # %entry
+; RV64ZBA-NEXT: addw a2, a0, a1
+; RV64ZBA-NEXT: add a0, a0, a1
+; RV64ZBA-NEXT: xor a0, a0, a2
+; RV64ZBA-NEXT: snez a0, a0
+; RV64ZBA-NEXT: xori a0, a0, 1
+; RV64ZBA-NEXT: ret
+;
+; RV64ZICOND-LABEL: saddo.not.i32:
+; RV64ZICOND: # %bb.0: # %entry
+; RV64ZICOND-NEXT: addw a2, a0, a1
+; RV64ZICOND-NEXT: add a0, a0, a1
+; RV64ZICOND-NEXT: xor a0, a0, a2
+; RV64ZICOND-NEXT: snez a0, a0
+; RV64ZICOND-NEXT: xori a0, a0, 1
+; RV64ZICOND-NEXT: ret
entry:
%t = call {i32, i1} @llvm.sadd.with.overflow.i32(i32 %v1, i32 %v2)
%obit = extractvalue {i32, i1} %t, 1
@@ -519,6 +1036,28 @@ define i64 @saddo.select.i64(i64 %v1, i64 %v2) {
; RV64-NEXT: mv a0, a1
; RV64-NEXT: .LBB30_2: # %entry
; RV64-NEXT: ret
+;
+; RV64ZBA-LABEL: saddo.select.i64:
+; RV64ZBA: # %bb.0: # %entry
+; RV64ZBA-NEXT: add a2, a0, a1
+; RV64ZBA-NEXT: slt a2, a2, a0
+; RV64ZBA-NEXT: slti a3, a1, 0
+; RV64ZBA-NEXT: bne a3, a2, .LBB30_2
+; RV64ZBA-NEXT: # %bb.1: # %entry
+; RV64ZBA-NEXT: mv a0, a1
+; RV64ZBA-NEXT: .LBB30_2: # %entry
+; RV64ZBA-NEXT: ret
+;
+; RV64ZICOND-LABEL: saddo.select.i64:
+; RV64ZICOND: # %bb.0: # %entry
+; RV64ZICOND-NEXT: add a2, a0, a1
+; RV64ZICOND-NEXT: slt a2, a2, a0
+; RV64ZICOND-NEXT: slti a3, a1, 0
+; RV64ZICOND-NEXT: xor a2, a3, a2
+; RV64ZICOND-NEXT: czero.nez a1, a1, a2
+; RV64ZICOND-NEXT: czero.eqz a0, a0, a2
+; RV64ZICOND-NEXT: or a0, a0, a1
+; RV64ZICOND-NEXT: ret
entry:
%t = call {i64, i1} @llvm.sadd.with.overflow.i64(i64 %v1, i64 %v2)
%obit = extractvalue {i64, i1} %t, 1
@@ -535,6 +1074,24 @@ define i1 @saddo.not.i64(i64 %v1, i64 %v2) {
; RV64-NEXT: xor a0, a1, a0
; RV64-NEXT: xori a0, a0, 1
; RV64-NEXT: ret
+;
+; RV64ZBA-LABEL: saddo.not.i64:
+; RV64ZBA: # %bb.0: # %entry
+; RV64ZBA-NEXT: add a2, a0, a1
+; RV64ZBA-NEXT: slt a0, a2, a0
+; RV64ZBA-NEXT: slti a1, a1, 0
+; RV64ZBA-NEXT: xor a0, a1, a0
+; RV64ZBA-NEXT: xori a0, a0, 1
+; RV64ZBA-NEXT: ret
+;
+; RV64ZICOND-LABEL: saddo.not.i64:
+; RV64ZICOND: # %bb.0: # %entry
+; RV64ZICOND-NEXT: add a2, a0, a1
+; RV64ZICOND-NEXT: slt a0, a2, a0
+; RV64ZICOND-NEXT: slti a1, a1, 0
+; RV64ZICOND-NEXT: xor a0, a1, a0
+; RV64ZICOND-NEXT: xori a0, a0, 1
+; RV64ZICOND-NEXT: ret
entry:
%t = call {i64, i1} @llvm.sadd.with.overflow.i64(i64 %v1, i64 %v2)
%obit = extractvalue {i64, i1} %t, 1
@@ -551,6 +1108,24 @@ define i32 @uaddo.select.i32(i32 signext %v1, i32 signext %v2) {
; RV64-NEXT: mv a0, a1
; RV64-NEXT: .LBB32_2: # %entry
; RV64-NEXT: ret
+;
+; RV64ZBA-LABEL: uaddo.select.i32:
+; RV64ZBA: # %bb.0: # %entry
+; RV64ZBA-NEXT: addw a2, a0, a1
+; RV64ZBA-NEXT: bltu a2, a0, .LBB32_2
+; RV64ZBA-NEXT: # %bb.1: # %entry
+; RV64ZBA-NEXT: mv a0, a1
+; RV64ZBA-NEXT: .LBB32_2: # %entry
+; RV64ZBA-NEXT: ret
+;
+; RV64ZICOND-LABEL: uaddo.select.i32:
+; RV64ZICOND: # %bb.0: # %entry
+; RV64ZICOND-NEXT: addw a2, a0, a1
+; RV64ZICOND-NEXT: sltu a2, a2, a0
+; RV64ZICOND-NEXT: czero.nez a1, a1, a2
+; RV64ZICOND-NEXT: czero.eqz a0, a0, a2
+; RV64ZICOND-NEXT: or a0, a0, a1
+; RV64ZICOND-NEXT: ret
entry:
%t = call {i32, i1} @llvm.uadd.with.overflow.i32(i32 %v1, i32 %v2)
%obit = extractvalue {i32, i1} %t, 1
@@ -565,6 +1140,20 @@ define i1 @uaddo.not.i32(i32 signext %v1, i32 signext %v2) {
; RV64-NEXT: sltu a0, a1, a0
; RV64-NEXT: xori a0, a0, 1
; RV64-NEXT: ret
+;
+; RV64ZBA-LABEL: uaddo.not.i32:
+; RV64ZBA: # %bb.0: # %entry
+; RV64ZBA-NEXT: addw a1, a0, a1
+; RV64ZBA-NEXT: sltu a0, a1, a0
+; RV64ZBA-NEXT: xori a0, a0, 1
+; RV64ZBA-NEXT: ret
+;
+; RV64ZICOND-LABEL: uaddo.not.i32:
+; RV64ZICOND: # %bb.0: # %entry
+; RV64ZICOND-NEXT: addw a1, a0, a1
+; RV64ZICOND-NEXT: sltu a0, a1, a0
+; RV64ZICOND-NEXT: xori a0, a0, 1
+; RV64ZICOND-NEXT: ret
entry:
%t = call {i32, i1} @llvm.uadd.with.overflow.i32(i32 %v1, i32 %v2)
%obit = extractvalue {i32, i1} %t, 1
@@ -581,6 +1170,24 @@ define i64 @uaddo.select.i64(i64 %v1, i64 %v2) {
; RV64-NEXT: mv a0, a1
; RV64-NEXT: .LBB34_2: # %entry
; RV64-NEXT: ret
+;
+; RV64ZBA-LABEL: uaddo.select.i64:
+; RV64ZBA: # %bb.0: # %entry
+; RV64ZBA-NEXT: add a2, a0, a1
+; RV64ZBA-NEXT: bltu a2, a0, .LBB34_2
+; RV64ZBA-NEXT: # %bb.1: # %entry
+; RV64ZBA-NEXT: mv a0, a1
+; RV64ZBA-NEXT: .LBB34_2: # %entry
+; RV64ZBA-NEXT: ret
+;
+; RV64ZICOND-LABEL: uaddo.select.i64:
+; RV64ZICOND: # %bb.0: # %entry
+; RV64ZICOND-NEXT: add a2, a0, a1
+; RV64ZICOND-NEXT: sltu a2, a2, a0
+; RV64ZICOND-NEXT: czero.nez a1, a1, a2
+; RV64ZICOND-NEXT: czero.eqz a0, a0, a2
+; RV64ZICOND-NEXT: or a0, a0, a1
+; RV64ZICOND-NEXT: ret
entry:
%t = call {i64, i1} @llvm.uadd.with.overflow.i64(i64 %v1, i64 %v2)
%obit = extractvalue {i64, i1} %t, 1
@@ -595,6 +1202,20 @@ define i1 @uaddo.not.i64(i64 %v1, i64 %v2) {
; RV64-NEXT: sltu a0, a1, a0
; RV64-NEXT: xori a0, a0, 1
; RV64-NEXT: ret
+;
+; RV64ZBA-LABEL: uaddo.not.i64:
+; RV64ZBA: # %bb.0: # %entry
+; RV64ZBA-NEXT: add a1, a0, a1
+; RV64ZBA-NEXT: sltu a0, a1, a0
+; RV64ZBA-NEXT: xori a0, a0, 1
+; RV64ZBA-NEXT: ret
+;
+; RV64ZICOND-LABEL: uaddo.not.i64:
+; RV64ZICOND: # %bb.0: # %entry
+; RV64ZICOND-NEXT: add a1, a0, a1
+; RV64ZICOND-NEXT: sltu a0, a1, a0
+; RV64ZICOND-NEXT: xori a0, a0, 1
+; RV64ZICOND-NEXT: ret
entry:
%t = call {i64, i1} @llvm.uadd.with.overflow.i64(i64 %v1, i64 %v2)
%obit = extractvalue {i64, i1} %t, 1
@@ -612,6 +1233,26 @@ define i32 @ssubo.select.i32(i32 signext %v1, i32 signext %v2) {
; RV64-NEXT: mv a0, a1
; RV64-NEXT: .LBB36_2: # %entry
; RV64-NEXT: ret
+;
+; RV64ZBA-LABEL: ssubo.select.i32:
+; RV64ZBA: # %bb.0: # %entry
+; RV64ZBA-NEXT: subw a2, a0, a1
+; RV64ZBA-NEXT: sub a3, a0, a1
+; RV64ZBA-NEXT: bne a3, a2, .LBB36_2
+; RV64ZBA-NEXT: # %bb.1: # %entry
+; RV64ZBA-NEXT: mv a0, a1
+; RV64ZBA-NEXT: .LBB36_2: # %entry
+; RV64ZBA-NEXT: ret
+;
+; RV64ZICOND-LABEL: ssubo.select.i32:
+; RV64ZICOND: # %bb.0: # %entry
+; RV64ZICOND-NEXT: subw a2, a0, a1
+; RV64ZICOND-NEXT: sub a3, a0, a1
+; RV64ZICOND-NEXT: xor a2, a3, a2
+; RV64ZICOND-NEXT: czero.nez a1, a1, a2
+; RV64ZICOND-NEXT: czero.eqz a0, a0, a2
+; RV64ZICOND-NEXT: or a0, a0, a1
+; RV64ZICOND-NEXT: ret
entry:
%t = call {i32, i1} @llvm.ssub.with.overflow.i32(i32 %v1, i32 %v2)
%obit = extractvalue {i32, i1} %t, 1
@@ -628,6 +1269,24 @@ define i1 @ssubo.not.i32(i32 signext %v1, i32 signext %v2) {
; RV64-NEXT: snez a0, a0
; RV64-NEXT: xori a0, a0, 1
; RV64-NEXT: ret
+;
+; RV64ZBA-LABEL: ssubo.not.i32:
+; RV64ZBA: # %bb.0: # %entry
+; RV64ZBA-NEXT: subw a2, a0, a1
+; RV64ZBA-NEXT: sub a0, a0, a1
+; RV64ZBA-NEXT: xor a0, a0, a2
+; RV64ZBA-NEXT: snez a0, a0
+; RV64ZBA-NEXT: xori a0, a0, 1
+; RV64ZBA-NEXT: ret
+;
+; RV64ZICOND-LABEL: ssubo.not.i32:
+; RV64ZICOND: # %bb.0: # %entry
+; RV64ZICOND-NEXT: subw a2, a0, a1
+; RV64ZICOND-NEXT: sub a0, a0, a1
+; RV64ZICOND-NEXT: xor a0, a0, a2
+; RV64ZICOND-NEXT: snez a0, a0
+; RV64ZICOND-NEXT: xori a0, a0, 1
+; RV64ZICOND-NEXT: ret
entry:
%t = call {i32, i1} @llvm.ssub.with.overflow.i32(i32 %v1, i32 %v2)
%obit = extractvalue {i32, i1} %t, 1
@@ -646,6 +1305,28 @@ define i64 @ssubo.select.i64(i64 %v1, i64 %v2) {
; RV64-NEXT: mv a0, a1
; RV64-NEXT: .LBB38_2: # %entry
; RV64-NEXT: ret
+;
+; RV64ZBA-LABEL: ssubo.select.i64:
+; RV64ZBA: # %bb.0: # %entry
+; RV64ZBA-NEXT: sgtz a2, a1
+; RV64ZBA-NEXT: sub a3, a0, a1
+; RV64ZBA-NEXT: slt a3, a3, a0
+; RV64ZBA-NEXT: bne a2, a3, .LBB38_2
+; RV64ZBA-NEXT: # %bb.1: # %entry
+; RV64ZBA-NEXT: mv a0, a1
+; RV64ZBA-NEXT: .LBB38_2: # %entry
+; RV64ZBA-NEXT: ret
+;
+; RV64ZICOND-LABEL: ssubo.select.i64:
+; RV64ZICOND: # %bb.0: # %entry
+; RV64ZICOND-NEXT: sgtz a2, a1
+; RV64ZICOND-NEXT: sub a3, a0, a1
+; RV64ZICOND-NEXT: slt a3, a3, a0
+; RV64ZICOND-NEXT: xor a2, a2, a3
+; RV64ZICOND-NEXT: czero.nez a1, a1, a2
+; RV64ZICOND-NEXT: czero.eqz a0, a0, a2
+; RV64ZICOND-NEXT: or a0, a0, a1
+; RV64ZICOND-NEXT: ret
entry:
%t = call {i64, i1} @llvm.ssub.with.overflow.i64(i64 %v1, i64 %v2)
%obit = extractvalue {i64, i1} %t, 1
@@ -662,6 +1343,24 @@ define i1 @ssub.not.i64(i64 %v1, i64 %v2) {
; RV64-NEXT: xor a0, a2, a0
; RV64-NEXT: xori a0, a0, 1
; RV64-NEXT: ret
+;
+; RV64ZBA-LABEL: ssub.not.i64:
+; RV64ZBA: # %bb.0: # %entry
+; RV64ZBA-NEXT: sgtz a2, a1
+; RV64ZBA-NEXT: sub a1, a0, a1
+; RV64ZBA-NEXT: slt a0, a1, a0
+; RV64ZBA-NEXT: xor a0, a2, a0
+; RV64ZBA-NEXT: xori a0, a0, 1
+; RV64ZBA-NEXT: ret
+;
+; RV64ZICOND-LABEL: ssub.not.i64:
+; RV64ZICOND: # %bb.0: # %entry
+; RV64ZICOND-NEXT: sgtz a2, a1
+; RV64ZICOND-NEXT: sub a1, a0, a1
+; RV64ZICOND-NEXT: slt a0, a1, a0
+; RV64ZICOND-NEXT: xor a0, a2, a0
+; RV64ZICOND-NEXT: xori a0, a0, 1
+; RV64ZICOND-NEXT: ret
entry:
%t = call {i64, i1} @llvm.ssub.with.overflow.i64(i64 %v1, i64 %v2)
%obit = extractvalue {i64, i1} %t, 1
@@ -678,6 +1377,24 @@ define i32 @usubo.select.i32(i32 signext %v1, i32 signext %v2) {
; RV64-NEXT: mv a0, a1
; RV64-NEXT: .LBB40_2: # %entry
; RV64-NEXT: ret
+;
+; RV64ZBA-LABEL: usubo.select.i32:
+; RV64ZBA: # %bb.0: # %entry
+; RV64ZBA-NEXT: subw a2, a0, a1
+; RV64ZBA-NEXT: bltu a0, a2, .LBB40_2
+; RV64ZBA-NEXT: # %bb.1: # %entry
+; RV64ZBA-NEXT: mv a0, a1
+; RV64ZBA-NEXT: .LBB40_2: # %entry
+; RV64ZBA-NEXT: ret
+;
+; RV64ZICOND-LABEL: usubo.select.i32:
+; RV64ZICOND: # %bb.0: # %entry
+; RV64ZICOND-NEXT: subw a2, a0, a1
+; RV64ZICOND-NEXT: sltu a2, a0, a2
+; RV64ZICOND-NEXT: czero.nez a1, a1, a2
+; RV64ZICOND-NEXT: czero.eqz a0, a0, a2
+; RV64ZICOND-NEXT: or a0, a0, a1
+; RV64ZICOND-NEXT: ret
entry:
%t = call {i32, i1} @llvm.usub.with.overflow.i32(i32 %v1, i32 %v2)
%obit = extractvalue {i32, i1} %t, 1
@@ -692,6 +1409,20 @@ define i1 @usubo.not.i32(i32 signext %v1, i32 signext %v2) {
; RV64-NEXT: sltu a0, a0, a1
; RV64-NEXT: xori a0, a0, 1
; RV64-NEXT: ret
+;
+; RV64ZBA-LABEL: usubo.not.i32:
+; RV64ZBA: # %bb.0: # %entry
+; RV64ZBA-NEXT: subw a1, a0, a1
+; RV64ZBA-NEXT: sltu a0, a0, a1
+; RV64ZBA-NEXT: xori a0, a0, 1
+; RV64ZBA-NEXT: ret
+;
+; RV64ZICOND-LABEL: usubo.not.i32:
+; RV64ZICOND: # %bb.0: # %entry
+; RV64ZICOND-NEXT: subw a1, a0, a1
+; RV64ZICOND-NEXT: sltu a0, a0, a1
+; RV64ZICOND-NEXT: xori a0, a0, 1
+; RV64ZICOND-NEXT: ret
entry:
%t = call {i32, i1} @llvm.usub.with.overflow.i32(i32 %v1, i32 %v2)
%obit = extractvalue {i32, i1} %t, 1
@@ -708,6 +1439,24 @@ define i64 @usubo.select.i64(i64 %v1, i64 %v2) {
; RV64-NEXT: mv a0, a1
; RV64-NEXT: .LBB42_2: # %entry
; RV64-NEXT: ret
+;
+; RV64ZBA-LABEL: usubo.select.i64:
+; RV64ZBA: # %bb.0: # %entry
+; RV64ZBA-NEXT: sub a2, a0, a1
+; RV64ZBA-NEXT: bltu a0, a2, .LBB42_2
+; RV64ZBA-NEXT: # %bb.1: # %entry
+; RV64ZBA-NEXT: mv a0, a1
+; RV64ZBA-NEXT: .LBB42_2: # %entry
+; RV64ZBA-NEXT: ret
+;
+; RV64ZICOND-LABEL: usubo.select.i64:
+; RV64ZICOND: # %bb.0: # %entry
+; RV64ZICOND-NEXT: sub a2, a0, a1
+; RV64ZICOND-NEXT: sltu a2, a0, a2
+; RV64ZICOND-NEXT: czero.nez a1, a1, a2
+; RV64ZICOND-NEXT: czero.eqz a0, a0, a2
+; RV64ZICOND-NEXT: or a0, a0, a1
+; RV64ZICOND-NEXT: ret
entry:
%t = call {i64, i1} @llvm.usub.with.overflow.i64(i64 %v1, i64 %v2)
%obit = extractvalue {i64, i1} %t, 1
@@ -722,6 +1471,20 @@ define i1 @usubo.not.i64(i64 %v1, i64 %v2) {
; RV64-NEXT: sltu a0, a0, a1
; RV64-NEXT: xori a0, a0, 1
; RV64-NEXT: ret
+;
+; RV64ZBA-LABEL: usubo.not.i64:
+; RV64ZBA: # %bb.0: # %entry
+; RV64ZBA-NEXT: sub a1, a0, a1
+; RV64ZBA-NEXT: sltu a0, a0, a1
+; RV64ZBA-NEXT: xori a0, a0, 1
+; RV64ZBA-NEXT: ret
+;
+; RV64ZICOND-LABEL: usubo.not.i64:
+; RV64ZICOND: # %bb.0: # %entry
+; RV64ZICOND-NEXT: sub a1, a0, a1
+; RV64ZICOND-NEXT: sltu a0, a0, a1
+; RV64ZICOND-NEXT: xori a0, a0, 1
+; RV64ZICOND-NEXT: ret
entry:
%t = call {i64, i1} @llvm.usub.with.overflow.i64(i64 %v1, i64 %v2)
%obit = extractvalue {i64, i1} %t, 1
@@ -739,6 +1502,26 @@ define i32 @smulo.select.i32(i32 signext %v1, i32 signext %v2) {
; RV64-NEXT: mv a0, a1
; RV64-NEXT: .LBB44_2: # %entry
; RV64-NEXT: ret
+;
+; RV64ZBA-LABEL: smulo.select.i32:
+; RV64ZBA: # %bb.0: # %entry
+; RV64ZBA-NEXT: mulw a2, a0, a1
+; RV64ZBA-NEXT: mul a3, a0, a1
+; RV64ZBA-NEXT: bne a3, a2, .LBB44_2
+; RV64ZBA-NEXT: # %bb.1: # %entry
+; RV64ZBA-NEXT: mv a0, a1
+; RV64ZBA-NEXT: .LBB44_2: # %entry
+; RV64ZBA-NEXT: ret
+;
+; RV64ZICOND-LABEL: smulo.select.i32:
+; RV64ZICOND: # %bb.0: # %entry
+; RV64ZICOND-NEXT: mulw a2, a0, a1
+; RV64ZICOND-NEXT: mul a3, a0, a1
+; RV64ZICOND-NEXT: xor a2, a3, a2
+; RV64ZICOND-NEXT: czero.nez a1, a1, a2
+; RV64ZICOND-NEXT: czero.eqz a0, a0, a2
+; RV64ZICOND-NEXT: or a0, a0, a1
+; RV64ZICOND-NEXT: ret
entry:
%t = call {i32, i1} @llvm.smul.with.overflow.i32(i32 %v1, i32 %v2)
%obit = extractvalue {i32, i1} %t, 1
@@ -755,6 +1538,24 @@ define i1 @smulo.not.i32(i32 signext %v1, i32 signext %v2) {
; RV64-NEXT: snez a0, a0
; RV64-NEXT: xori a0, a0, 1
; RV64-NEXT: ret
+;
+; RV64ZBA-LABEL: smulo.not.i32:
+; RV64ZBA: # %bb.0: # %entry
+; RV64ZBA-NEXT: mulw a2, a0, a1
+; RV64ZBA-NEXT: mul a0, a0, a1
+; RV64ZBA-NEXT: xor a0, a0, a2
+; RV64ZBA-NEXT: snez a0, a0
+; RV64ZBA-NEXT: xori a0, a0, 1
+; RV64ZBA-NEXT: ret
+;
+; RV64ZICOND-LABEL: smulo.not.i32:
+; RV64ZICOND: # %bb.0: # %entry
+; RV64ZICOND-NEXT: mulw a2, a0, a1
+; RV64ZICOND-NEXT: mul a0, a0, a1
+; RV64ZICOND-NEXT: xor a0, a0, a2
+; RV64ZICOND-NEXT: snez a0, a0
+; RV64ZICOND-NEXT: xori a0, a0, 1
+; RV64ZICOND-NEXT: ret
entry:
%t = call {i32, i1} @llvm.smul.with.overflow.i32(i32 %v1, i32 %v2)
%obit = extractvalue {i32, i1} %t, 1
@@ -773,6 +1574,28 @@ define i64 @smulo.select.i64(i64 %v1, i64 %v2) {
; RV64-NEXT: mv a0, a1
; RV64-NEXT: .LBB46_2: # %entry
; RV64-NEXT: ret
+;
+; RV64ZBA-LABEL: smulo.select.i64:
+; RV64ZBA: # %bb.0: # %entry
+; RV64ZBA-NEXT: mulh a2, a0, a1
+; RV64ZBA-NEXT: mul a3, a0, a1
+; RV64ZBA-NEXT: srai a3, a3, 63
+; RV64ZBA-NEXT: bne a2, a3, .LBB46_2
+; RV64ZBA-NEXT: # %bb.1: # %entry
+; RV64ZBA-NEXT: mv a0, a1
+; RV64ZBA-NEXT: .LBB46_2: # %entry
+; RV64ZBA-NEXT: ret
+;
+; RV64ZICOND-LABEL: smulo.select.i64:
+; RV64ZICOND: # %bb.0: # %entry
+; RV64ZICOND-NEXT: mulh a2, a0, a1
+; RV64ZICOND-NEXT: mul a3, a0, a1
+; RV64ZICOND-NEXT: srai a3, a3, 63
+; RV64ZICOND-NEXT: xor a2, a2, a3
+; RV64ZICOND-NEXT: czero.nez a1, a1, a2
+; RV64ZICOND-NEXT: czero.eqz a0, a0, a2
+; RV64ZICOND-NEXT: or a0, a0, a1
+; RV64ZICOND-NEXT: ret
entry:
%t = call {i64, i1} @llvm.smul.with.overflow.i64(i64 %v1, i64 %v2)
%obit = extractvalue {i64, i1} %t, 1
@@ -790,6 +1613,26 @@ define i1 @smulo.not.i64(i64 %v1, i64 %v2) {
; RV64-NEXT: snez a0, a0
; RV64-NEXT: xori a0, a0, 1
; RV64-NEXT: ret
+;
+; RV64ZBA-LABEL: smulo.not.i64:
+; RV64ZBA: # %bb.0: # %entry
+; RV64ZBA-NEXT: mulh a2, a0, a1
+; RV64ZBA-NEXT: mul a0, a0, a1
+; RV64ZBA-NEXT: srai a0, a0, 63
+; RV64ZBA-NEXT: xor a0, a2, a0
+; RV64ZBA-NEXT: snez a0, a0
+; RV64ZBA-NEXT: xori a0, a0, 1
+; RV64ZBA-NEXT: ret
+;
+; RV64ZICOND-LABEL: smulo.not.i64:
+; RV64ZICOND: # %bb.0: # %entry
+; RV64ZICOND-NEXT: mulh a2, a0, a1
+; RV64ZICOND-NEXT: mul a0, a0, a1
+; RV64ZICOND-NEXT: srai a0, a0, 63
+; RV64ZICOND-NEXT: xor a0, a2, a0
+; RV64ZICOND-NEXT: snez a0, a0
+; RV64ZICOND-NEXT: xori a0, a0, 1
+; RV64ZICOND-NEXT: ret
entry:
%t = call {i64, i1} @llvm.smul.with.overflow.i64(i64 %v1, i64 %v2)
%obit = extractvalue {i64, i1} %t, 1
@@ -809,6 +1652,29 @@ define i32 @umulo.select.i32(i32 signext %v1, i32 signext %v2) {
; RV64-NEXT: mv a0, a1
; RV64-NEXT: .LBB48_2: # %entry
; RV64-NEXT: ret
+;
+; RV64ZBA-LABEL: umulo.select.i32:
+; RV64ZBA: # %bb.0: # %entry
+; RV64ZBA-NEXT: zext.w a2, a1
+; RV64ZBA-NEXT: zext.w a3, a0
+; RV64ZBA-NEXT: mul a2, a3, a2
+; RV64ZBA-NEXT: srai a2, a2, 32
+; RV64ZBA-NEXT: bnez a2, .LBB48_2
+; RV64ZBA-NEXT: # %bb.1: # %entry
+; RV64ZBA-NEXT: mv a0, a1
+; RV64ZBA-NEXT: .LBB48_2: # %entry
+; RV64ZBA-NEXT: ret
+;
+; RV64ZICOND-LABEL: umulo.select.i32:
+; RV64ZICOND: # %bb.0: # %entry
+; RV64ZICOND-NEXT: slli a2, a1, 32
+; RV64ZICOND-NEXT: slli a3, a0, 32
+; RV64ZICOND-NEXT: mulhu a2, a3, a2
+; RV64ZICOND-NEXT: srai a2, a2, 32
+; RV64ZICOND-NEXT: czero.nez a1, a1, a2
+; RV64ZICOND-NEXT: czero.eqz a0, a0, a2
+; RV64ZICOND-NEXT: or a0, a0, a1
+; RV64ZICOND-NEXT: ret
entry:
%t = call {i32, i1} @llvm.umul.with.overflow.i32(i32 %v1, i32 %v2)
%obit = extractvalue {i32, i1} %t, 1
@@ -826,6 +1692,26 @@ define i1 @umulo.not.i32(i32 signext %v1, i32 signext %v2) {
; RV64-NEXT: snez a0, a0
; RV64-NEXT: xori a0, a0, 1
; RV64-NEXT: ret
+;
+; RV64ZBA-LABEL: umulo.not.i32:
+; RV64ZBA: # %bb.0: # %entry
+; RV64ZBA-NEXT: zext.w a1, a1
+; RV64ZBA-NEXT: zext.w a0, a0
+; RV64ZBA-NEXT: mul a0, a0, a1
+; RV64ZBA-NEXT: srai a0, a0, 32
+; RV64ZBA-NEXT: snez a0, a0
+; RV64ZBA-NEXT: xori a0, a0, 1
+; RV64ZBA-NEXT: ret
+;
+; RV64ZICOND-LABEL: umulo.not.i32:
+; RV64ZICOND: # %bb.0: # %entry
+; RV64ZICOND-NEXT: slli a1, a1, 32
+; RV64ZICOND-NEXT: slli a0, a0, 32
+; RV64ZICOND-NEXT: mulhu a0, a0, a1
+; RV64ZICOND-NEXT: srai a0, a0, 32
+; RV64ZICOND-NEXT: snez a0, a0
+; RV64ZICOND-NEXT: xori a0, a0, 1
+; RV64ZICOND-NEXT: ret
entry:
%t = call {i32, i1} @llvm.umul.with.overflow.i32(i32 %v1, i32 %v2)
%obit = extractvalue {i32, i1} %t, 1
@@ -842,6 +1728,23 @@ define i64 @umulo.select.i64(i64 %v1, i64 %v2) {
; RV64-NEXT: mv a0, a1
; RV64-NEXT: .LBB50_2: # %entry
; RV64-NEXT: ret
+;
+; RV64ZBA-LABEL: umulo.select.i64:
+; RV64ZBA: # %bb.0: # %entry
+; RV64ZBA-NEXT: mulhu a2, a0, a1
+; RV64ZBA-NEXT: bnez a2, .LBB50_2
+; RV64ZBA-NEXT: # %bb.1: # %entry
+; RV64ZBA-NEXT: mv a0, a1
+; RV64ZBA-NEXT: .LBB50_2: # %entry
+; RV64ZBA-NEXT: ret
+;
+; RV64ZICOND-LABEL: umulo.select.i64:
+; RV64ZICOND: # %bb.0: # %entry
+; RV64ZICOND-NEXT: mulhu a2, a0, a1
+; RV64ZICOND-NEXT: czero.nez a1, a1, a2
+; RV64ZICOND-NEXT: czero.eqz a0, a0, a2
+; RV64ZICOND-NEXT: or a0, a0, a1
+; RV64ZICOND-NEXT: ret
entry:
%t = call {i64, i1} @llvm.umul.with.overflow.i64(i64 %v1, i64 %v2)
%obit = extractvalue {i64, i1} %t, 1
@@ -856,6 +1759,20 @@ define i1 @umulo.not.i64(i64 %v1, i64 %v2) {
; RV64-NEXT: snez a0, a0
; RV64-NEXT: xori a0, a0, 1
; RV64-NEXT: ret
+;
+; RV64ZBA-LABEL: umulo.not.i64:
+; RV64ZBA: # %bb.0: # %entry
+; RV64ZBA-NEXT: mulhu a0, a0, a1
+; RV64ZBA-NEXT: snez a0, a0
+; RV64ZBA-NEXT: xori a0, a0, 1
+; RV64ZBA-NEXT: ret
+;
+; RV64ZICOND-LABEL: umulo.not.i64:
+; RV64ZICOND: # %bb.0: # %entry
+; RV64ZICOND-NEXT: mulhu a0, a0, a1
+; RV64ZICOND-NEXT: snez a0, a0
+; RV64ZICOND-NEXT: xori a0, a0, 1
+; RV64ZICOND-NEXT: ret
entry:
%t = call {i64, i1} @llvm.umul.with.overflow.i64(i64 %v1, i64 %v2)
%obit = extractvalue {i64, i1} %t, 1
@@ -879,6 +1796,30 @@ define zeroext i1 @saddo.br.i32(i32 signext %v1, i32 signext %v2) {
; RV64-NEXT: .LBB52_2: # %continue
; RV64-NEXT: li a0, 1
; RV64-NEXT: ret
+;
+; RV64ZBA-LABEL: saddo.br.i32:
+; RV64ZBA: # %bb.0: # %entry
+; RV64ZBA-NEXT: addw a2, a0, a1
+; RV64ZBA-NEXT: add a0, a0, a1
+; RV64ZBA-NEXT: beq a0, a2, .LBB52_2
+; RV64ZBA-NEXT: # %bb.1: # %overflow
+; RV64ZBA-NEXT: li a0, 0
+; RV64ZBA-NEXT: ret
+; RV64ZBA-NEXT: .LBB52_2: # %continue
+; RV64ZBA-NEXT: li a0, 1
+; RV64ZBA-NEXT: ret
+;
+; RV64ZICOND-LABEL: saddo.br.i32:
+; RV64ZICOND: # %bb.0: # %entry
+; RV64ZICOND-NEXT: addw a2, a0, a1
+; RV64ZICOND-NEXT: add a0, a0, a1
+; RV64ZICOND-NEXT: beq a0, a2, .LBB52_2
+; RV64ZICOND-NEXT: # %bb.1: # %overflow
+; RV64ZICOND-NEXT: li a0, 0
+; RV64ZICOND-NEXT: ret
+; RV64ZICOND-NEXT: .LBB52_2: # %continue
+; RV64ZICOND-NEXT: li a0, 1
+; RV64ZICOND-NEXT: ret
entry:
%t = call {i32, i1} @llvm.sadd.with.overflow.i32(i32 %v1, i32 %v2)
%val = extractvalue {i32, i1} %t, 0
@@ -905,6 +1846,32 @@ define zeroext i1 @saddo.br.i64(i64 %v1, i64 %v2) {
; RV64-NEXT: .LBB53_2: # %continue
; RV64-NEXT: li a0, 1
; RV64-NEXT: ret
+;
+; RV64ZBA-LABEL: saddo.br.i64:
+; RV64ZBA: # %bb.0: # %entry
+; RV64ZBA-NEXT: add a2, a0, a1
+; RV64ZBA-NEXT: slt a0, a2, a0
+; RV64ZBA-NEXT: slti a1, a1, 0
+; RV64ZBA-NEXT: beq a1, a0, .LBB53_2
+; RV64ZBA-NEXT: # %bb.1: # %overflow
+; RV64ZBA-NEXT: li a0, 0
+; RV64ZBA-NEXT: ret
+; RV64ZBA-NEXT: .LBB53_2: # %continue
+; RV64ZBA-NEXT: li a0, 1
+; RV64ZBA-NEXT: ret
+;
+; RV64ZICOND-LABEL: saddo.br.i64:
+; RV64ZICOND: # %bb.0: # %entry
+; RV64ZICOND-NEXT: add a2, a0, a1
+; RV64ZICOND-NEXT: slt a0, a2, a0
+; RV64ZICOND-NEXT: slti a1, a1, 0
+; RV64ZICOND-NEXT: beq a1, a0, .LBB53_2
+; RV64ZICOND-NEXT: # %bb.1: # %overflow
+; RV64ZICOND-NEXT: li a0, 0
+; RV64ZICOND-NEXT: ret
+; RV64ZICOND-NEXT: .LBB53_2: # %continue
+; RV64ZICOND-NEXT: li a0, 1
+; RV64ZICOND-NEXT: ret
entry:
%t = call {i64, i1} @llvm.sadd.with.overflow.i64(i64 %v1, i64 %v2)
%val = extractvalue {i64, i1} %t, 0
@@ -930,6 +1897,30 @@ define zeroext i1 @uaddo.br.i32(i32 %v1, i32 %v2) {
; RV64-NEXT: .LBB54_2: # %continue
; RV64-NEXT: li a0, 1
; RV64-NEXT: ret
+;
+; RV64ZBA-LABEL: uaddo.br.i32:
+; RV64ZBA: # %bb.0: # %entry
+; RV64ZBA-NEXT: addw a1, a0, a1
+; RV64ZBA-NEXT: sext.w a0, a0
+; RV64ZBA-NEXT: bgeu a1, a0, .LBB54_2
+; RV64ZBA-NEXT: # %bb.1: # %overflow
+; RV64ZBA-NEXT: li a0, 0
+; RV64ZBA-NEXT: ret
+; RV64ZBA-NEXT: .LBB54_2: # %continue
+; RV64ZBA-NEXT: li a0, 1
+; RV64ZBA-NEXT: ret
+;
+; RV64ZICOND-LABEL: uaddo.br.i32:
+; RV64ZICOND: # %bb.0: # %entry
+; RV64ZICOND-NEXT: addw a1, a0, a1
+; RV64ZICOND-NEXT: sext.w a0, a0
+; RV64ZICOND-NEXT: bgeu a1, a0, .LBB54_2
+; RV64ZICOND-NEXT: # %bb.1: # %overflow
+; RV64ZICOND-NEXT: li a0, 0
+; RV64ZICOND-NEXT: ret
+; RV64ZICOND-NEXT: .LBB54_2: # %continue
+; RV64ZICOND-NEXT: li a0, 1
+; RV64ZICOND-NEXT: ret
entry:
%t = call {i32, i1} @llvm.uadd.with.overflow.i32(i32 %v1, i32 %v2)
%val = extractvalue {i32, i1} %t, 0
@@ -954,6 +1945,28 @@ define zeroext i1 @uaddo.br.i64(i64 %v1, i64 %v2) {
; RV64-NEXT: .LBB55_2: # %continue
; RV64-NEXT: li a0, 1
; RV64-NEXT: ret
+;
+; RV64ZBA-LABEL: uaddo.br.i64:
+; RV64ZBA: # %bb.0: # %entry
+; RV64ZBA-NEXT: add a1, a0, a1
+; RV64ZBA-NEXT: bgeu a1, a0, .LBB55_2
+; RV64ZBA-NEXT: # %bb.1: # %overflow
+; RV64ZBA-NEXT: li a0, 0
+; RV64ZBA-NEXT: ret
+; RV64ZBA-NEXT: .LBB55_2: # %continue
+; RV64ZBA-NEXT: li a0, 1
+; RV64ZBA-NEXT: ret
+;
+; RV64ZICOND-LABEL: uaddo.br.i64:
+; RV64ZICOND: # %bb.0: # %entry
+; RV64ZICOND-NEXT: add a1, a0, a1
+; RV64ZICOND-NEXT: bgeu a1, a0, .LBB55_2
+; RV64ZICOND-NEXT: # %bb.1: # %overflow
+; RV64ZICOND-NEXT: li a0, 0
+; RV64ZICOND-NEXT: ret
+; RV64ZICOND-NEXT: .LBB55_2: # %continue
+; RV64ZICOND-NEXT: li a0, 1
+; RV64ZICOND-NEXT: ret
entry:
%t = call {i64, i1} @llvm.uadd.with.overflow.i64(i64 %v1, i64 %v2)
%val = extractvalue {i64, i1} %t, 0
@@ -979,6 +1992,30 @@ define zeroext i1 @ssubo.br.i32(i32 signext %v1, i32 signext %v2) {
; RV64-NEXT: .LBB56_2: # %continue
; RV64-NEXT: li a0, 1
; RV64-NEXT: ret
+;
+; RV64ZBA-LABEL: ssubo.br.i32:
+; RV64ZBA: # %bb.0: # %entry
+; RV64ZBA-NEXT: subw a2, a0, a1
+; RV64ZBA-NEXT: sub a0, a0, a1
+; RV64ZBA-NEXT: beq a0, a2, .LBB56_2
+; RV64ZBA-NEXT: # %bb.1: # %overflow
+; RV64ZBA-NEXT: li a0, 0
+; RV64ZBA-NEXT: ret
+; RV64ZBA-NEXT: .LBB56_2: # %continue
+; RV64ZBA-NEXT: li a0, 1
+; RV64ZBA-NEXT: ret
+;
+; RV64ZICOND-LABEL: ssubo.br.i32:
+; RV64ZICOND: # %bb.0: # %entry
+; RV64ZICOND-NEXT: subw a2, a0, a1
+; RV64ZICOND-NEXT: sub a0, a0, a1
+; RV64ZICOND-NEXT: beq a0, a2, .LBB56_2
+; RV64ZICOND-NEXT: # %bb.1: # %overflow
+; RV64ZICOND-NEXT: li a0, 0
+; RV64ZICOND-NEXT: ret
+; RV64ZICOND-NEXT: .LBB56_2: # %continue
+; RV64ZICOND-NEXT: li a0, 1
+; RV64ZICOND-NEXT: ret
entry:
%t = call {i32, i1} @llvm.ssub.with.overflow.i32(i32 %v1, i32 %v2)
%val = extractvalue {i32, i1} %t, 0
@@ -1005,6 +2042,32 @@ define zeroext i1 @ssubo.br.i64(i64 %v1, i64 %v2) {
; RV64-NEXT: .LBB57_2: # %continue
; RV64-NEXT: li a0, 1
; RV64-NEXT: ret
+;
+; RV64ZBA-LABEL: ssubo.br.i64:
+; RV64ZBA: # %bb.0: # %entry
+; RV64ZBA-NEXT: sgtz a2, a1
+; RV64ZBA-NEXT: sub a1, a0, a1
+; RV64ZBA-NEXT: slt a0, a1, a0
+; RV64ZBA-NEXT: beq a2, a0, .LBB57_2
+; RV64ZBA-NEXT: # %bb.1: # %overflow
+; RV64ZBA-NEXT: li a0, 0
+; RV64ZBA-NEXT: ret
+; RV64ZBA-NEXT: .LBB57_2: # %continue
+; RV64ZBA-NEXT: li a0, 1
+; RV64ZBA-NEXT: ret
+;
+; RV64ZICOND-LABEL: ssubo.br.i64:
+; RV64ZICOND: # %bb.0: # %entry
+; RV64ZICOND-NEXT: sgtz a2, a1
+; RV64ZICOND-NEXT: sub a1, a0, a1
+; RV64ZICOND-NEXT: slt a0, a1, a0
+; RV64ZICOND-NEXT: beq a2, a0, .LBB57_2
+; RV64ZICOND-NEXT: # %bb.1: # %overflow
+; RV64ZICOND-NEXT: li a0, 0
+; RV64ZICOND-NEXT: ret
+; RV64ZICOND-NEXT: .LBB57_2: # %continue
+; RV64ZICOND-NEXT: li a0, 1
+; RV64ZICOND-NEXT: ret
entry:
%t = call {i64, i1} @llvm.ssub.with.overflow.i64(i64 %v1, i64 %v2)
%val = extractvalue {i64, i1} %t, 0
@@ -1029,6 +2092,28 @@ define zeroext i1 @usubo.br.i32(i32 signext %v1, i32 signext %v2) {
; RV64-NEXT: .LBB58_2: # %continue
; RV64-NEXT: li a0, 1
; RV64-NEXT: ret
+;
+; RV64ZBA-LABEL: usubo.br.i32:
+; RV64ZBA: # %bb.0: # %entry
+; RV64ZBA-NEXT: subw a1, a0, a1
+; RV64ZBA-NEXT: bgeu a0, a1, .LBB58_2
+; RV64ZBA-NEXT: # %bb.1: # %overflow
+; RV64ZBA-NEXT: li a0, 0
+; RV64ZBA-NEXT: ret
+; RV64ZBA-NEXT: .LBB58_2: # %continue
+; RV64ZBA-NEXT: li a0, 1
+; RV64ZBA-NEXT: ret
+;
+; RV64ZICOND-LABEL: usubo.br.i32:
+; RV64ZICOND: # %bb.0: # %entry
+; RV64ZICOND-NEXT: subw a1, a0, a1
+; RV64ZICOND-NEXT: bgeu a0, a1, .LBB58_2
+; RV64ZICOND-NEXT: # %bb.1: # %overflow
+; RV64ZICOND-NEXT: li a0, 0
+; RV64ZICOND-NEXT: ret
+; RV64ZICOND-NEXT: .LBB58_2: # %continue
+; RV64ZICOND-NEXT: li a0, 1
+; RV64ZICOND-NEXT: ret
entry:
%t = call {i32, i1} @llvm.usub.with.overflow.i32(i32 %v1, i32 %v2)
%val = extractvalue {i32, i1} %t, 0
@@ -1053,6 +2138,28 @@ define zeroext i1 @usubo.br.i64(i64 %v1, i64 %v2) {
; RV64-NEXT: .LBB59_2: # %continue
; RV64-NEXT: li a0, 1
; RV64-NEXT: ret
+;
+; RV64ZBA-LABEL: usubo.br.i64:
+; RV64ZBA: # %bb.0: # %entry
+; RV64ZBA-NEXT: sub a1, a0, a1
+; RV64ZBA-NEXT: bgeu a0, a1, .LBB59_2
+; RV64ZBA-NEXT: # %bb.1: # %overflow
+; RV64ZBA-NEXT: li a0, 0
+; RV64ZBA-NEXT: ret
+; RV64ZBA-NEXT: .LBB59_2: # %continue
+; RV64ZBA-NEXT: li a0, 1
+; RV64ZBA-NEXT: ret
+;
+; RV64ZICOND-LABEL: usubo.br.i64:
+; RV64ZICOND: # %bb.0: # %entry
+; RV64ZICOND-NEXT: sub a1, a0, a1
+; RV64ZICOND-NEXT: bgeu a0, a1, .LBB59_2
+; RV64ZICOND-NEXT: # %bb.1: # %overflow
+; RV64ZICOND-NEXT: li a0, 0
+; RV64ZICOND-NEXT: ret
+; RV64ZICOND-NEXT: .LBB59_2: # %continue
+; RV64ZICOND-NEXT: li a0, 1
+; RV64ZICOND-NEXT: ret
entry:
%t = call {i64, i1} @llvm.usub.with.overflow.i64(i64 %v1, i64 %v2)
%val = extractvalue {i64, i1} %t, 0
@@ -1078,6 +2185,30 @@ define zeroext i1 @smulo.br.i32(i32 signext %v1, i32 signext %v2) {
; RV64-NEXT: .LBB60_2: # %continue
; RV64-NEXT: li a0, 1
; RV64-NEXT: ret
+;
+; RV64ZBA-LABEL: smulo.br.i32:
+; RV64ZBA: # %bb.0: # %entry
+; RV64ZBA-NEXT: mulw a2, a0, a1
+; RV64ZBA-NEXT: mul a0, a0, a1
+; RV64ZBA-NEXT: beq a0, a2, .LBB60_2
+; RV64ZBA-NEXT: # %bb.1: # %overflow
+; RV64ZBA-NEXT: li a0, 0
+; RV64ZBA-NEXT: ret
+; RV64ZBA-NEXT: .LBB60_2: # %continue
+; RV64ZBA-NEXT: li a0, 1
+; RV64ZBA-NEXT: ret
+;
+; RV64ZICOND-LABEL: smulo.br.i32:
+; RV64ZICOND: # %bb.0: # %entry
+; RV64ZICOND-NEXT: mulw a2, a0, a1
+; RV64ZICOND-NEXT: mul a0, a0, a1
+; RV64ZICOND-NEXT: beq a0, a2, .LBB60_2
+; RV64ZICOND-NEXT: # %bb.1: # %overflow
+; RV64ZICOND-NEXT: li a0, 0
+; RV64ZICOND-NEXT: ret
+; RV64ZICOND-NEXT: .LBB60_2: # %continue
+; RV64ZICOND-NEXT: li a0, 1
+; RV64ZICOND-NEXT: ret
entry:
%t = call {i32, i1} @llvm.smul.with.overflow.i32(i32 %v1, i32 %v2)
%val = extractvalue {i32, i1} %t, 0
@@ -1104,6 +2235,32 @@ define zeroext i1 @smulo.br.i64(i64 %v1, i64 %v2) {
; RV64-NEXT: .LBB61_2: # %continue
; RV64-NEXT: li a0, 1
; RV64-NEXT: ret
+;
+; RV64ZBA-LABEL: smulo.br.i64:
+; RV64ZBA: # %bb.0: # %entry
+; RV64ZBA-NEXT: mulh a2, a0, a1
+; RV64ZBA-NEXT: mul a0, a0, a1
+; RV64ZBA-NEXT: srai a0, a0, 63
+; RV64ZBA-NEXT: beq a2, a0, .LBB61_2
+; RV64ZBA-NEXT: # %bb.1: # %overflow
+; RV64ZBA-NEXT: li a0, 0
+; RV64ZBA-NEXT: ret
+; RV64ZBA-NEXT: .LBB61_2: # %continue
+; RV64ZBA-NEXT: li a0, 1
+; RV64ZBA-NEXT: ret
+;
+; RV64ZICOND-LABEL: smulo.br.i64:
+; RV64ZICOND: # %bb.0: # %entry
+; RV64ZICOND-NEXT: mulh a2, a0, a1
+; RV64ZICOND-NEXT: mul a0, a0, a1
+; RV64ZICOND-NEXT: srai a0, a0, 63
+; RV64ZICOND-NEXT: beq a2, a0, .LBB61_2
+; RV64ZICOND-NEXT: # %bb.1: # %overflow
+; RV64ZICOND-NEXT: li a0, 0
+; RV64ZICOND-NEXT: ret
+; RV64ZICOND-NEXT: .LBB61_2: # %continue
+; RV64ZICOND-NEXT: li a0, 1
+; RV64ZICOND-NEXT: ret
entry:
%t = call {i64, i1} @llvm.smul.with.overflow.i64(i64 %v1, i64 %v2)
%val = extractvalue {i64, i1} %t, 0
@@ -1131,6 +2288,34 @@ define zeroext i1 @smulo2.br.i64(i64 %v1) {
; RV64-NEXT: .LBB62_2: # %continue
; RV64-NEXT: li a0, 1
; RV64-NEXT: ret
+;
+; RV64ZBA-LABEL: smulo2.br.i64:
+; RV64ZBA: # %bb.0: # %entry
+; RV64ZBA-NEXT: li a1, -13
+; RV64ZBA-NEXT: mulh a2, a0, a1
+; RV64ZBA-NEXT: mul a0, a0, a1
+; RV64ZBA-NEXT: srai a0, a0, 63
+; RV64ZBA-NEXT: beq a2, a0, .LBB62_2
+; RV64ZBA-NEXT: # %bb.1: # %overflow
+; RV64ZBA-NEXT: li a0, 0
+; RV64ZBA-NEXT: ret
+; RV64ZBA-NEXT: .LBB62_2: # %continue
+; RV64ZBA-NEXT: li a0, 1
+; RV64ZBA-NEXT: ret
+;
+; RV64ZICOND-LABEL: smulo2.br.i64:
+; RV64ZICOND: # %bb.0: # %entry
+; RV64ZICOND-NEXT: li a1, -13
+; RV64ZICOND-NEXT: mulh a2, a0, a1
+; RV64ZICOND-NEXT: mul a0, a0, a1
+; RV64ZICOND-NEXT: srai a0, a0, 63
+; RV64ZICOND-NEXT: beq a2, a0, .LBB62_2
+; RV64ZICOND-NEXT: # %bb.1: # %overflow
+; RV64ZICOND-NEXT: li a0, 0
+; RV64ZICOND-NEXT: ret
+; RV64ZICOND-NEXT: .LBB62_2: # %continue
+; RV64ZICOND-NEXT: li a0, 1
+; RV64ZICOND-NEXT: ret
entry:
%t = call {i64, i1} @llvm.smul.with.overflow.i64(i64 %v1, i64 -13)
%val = extractvalue {i64, i1} %t, 0
@@ -1158,6 +2343,34 @@ define zeroext i1 @umulo.br.i32(i32 signext %v1, i32 signext %v2) {
; RV64-NEXT: .LBB63_2: # %continue
; RV64-NEXT: li a0, 1
; RV64-NEXT: ret
+;
+; RV64ZBA-LABEL: umulo.br.i32:
+; RV64ZBA: # %bb.0: # %entry
+; RV64ZBA-NEXT: zext.w a1, a1
+; RV64ZBA-NEXT: zext.w a0, a0
+; RV64ZBA-NEXT: mul a0, a0, a1
+; RV64ZBA-NEXT: srai a0, a0, 32
+; RV64ZBA-NEXT: beqz a0, .LBB63_2
+; RV64ZBA-NEXT: # %bb.1: # %overflow
+; RV64ZBA-NEXT: li a0, 0
+; RV64ZBA-NEXT: ret
+; RV64ZBA-NEXT: .LBB63_2: # %continue
+; RV64ZBA-NEXT: li a0, 1
+; RV64ZBA-NEXT: ret
+;
+; RV64ZICOND-LABEL: umulo.br.i32:
+; RV64ZICOND: # %bb.0: # %entry
+; RV64ZICOND-NEXT: slli a1, a1, 32
+; RV64ZICOND-NEXT: slli a0, a0, 32
+; RV64ZICOND-NEXT: mulhu a0, a0, a1
+; RV64ZICOND-NEXT: srai a0, a0, 32
+; RV64ZICOND-NEXT: beqz a0, .LBB63_2
+; RV64ZICOND-NEXT: # %bb.1: # %overflow
+; RV64ZICOND-NEXT: li a0, 0
+; RV64ZICOND-NEXT: ret
+; RV64ZICOND-NEXT: .LBB63_2: # %continue
+; RV64ZICOND-NEXT: li a0, 1
+; RV64ZICOND-NEXT: ret
entry:
%t = call {i32, i1} @llvm.umul.with.overflow.i32(i32 %v1, i32 %v2)
%val = extractvalue {i32, i1} %t, 0
@@ -1182,6 +2395,28 @@ define zeroext i1 @umulo.br.i64(i64 %v1, i64 %v2) {
; RV64-NEXT: .LBB64_2: # %continue
; RV64-NEXT: li a0, 1
; RV64-NEXT: ret
+;
+; RV64ZBA-LABEL: umulo.br.i64:
+; RV64ZBA: # %bb.0: # %entry
+; RV64ZBA-NEXT: mulhu a0, a0, a1
+; RV64ZBA-NEXT: beqz a0, .LBB64_2
+; RV64ZBA-NEXT: # %bb.1: # %overflow
+; RV64ZBA-NEXT: li a0, 0
+; RV64ZBA-NEXT: ret
+; RV64ZBA-NEXT: .LBB64_2: # %continue
+; RV64ZBA-NEXT: li a0, 1
+; RV64ZBA-NEXT: ret
+;
+; RV64ZICOND-LABEL: umulo.br.i64:
+; RV64ZICOND: # %bb.0: # %entry
+; RV64ZICOND-NEXT: mulhu a0, a0, a1
+; RV64ZICOND-NEXT: beqz a0, .LBB64_2
+; RV64ZICOND-NEXT: # %bb.1: # %overflow
+; RV64ZICOND-NEXT: li a0, 0
+; RV64ZICOND-NEXT: ret
+; RV64ZICOND-NEXT: .LBB64_2: # %continue
+; RV64ZICOND-NEXT: li a0, 1
+; RV64ZICOND-NEXT: ret
entry:
%t = call {i64, i1} @llvm.umul.with.overflow.i64(i64 %v1, i64 %v2)
%val = extractvalue {i64, i1} %t, 0
@@ -1206,6 +2441,28 @@ define zeroext i1 @umulo2.br.i64(i64 %v1) {
; RV64-NEXT: .LBB65_2: # %continue
; RV64-NEXT: li a0, 1
; RV64-NEXT: ret
+;
+; RV64ZBA-LABEL: umulo2.br.i64:
+; RV64ZBA: # %bb.0: # %entry
+; RV64ZBA-NEXT: add a1, a0, a0
+; RV64ZBA-NEXT: bgeu a1, a0, .LBB65_2
+; RV64ZBA-NEXT: # %bb.1: # %overflow
+; RV64ZBA-NEXT: li a0, 0
+; RV64ZBA-NEXT: ret
+; RV64ZBA-NEXT: .LBB65_2: # %continue
+; RV64ZBA-NEXT: li a0, 1
+; RV64ZBA-NEXT: ret
+;
+; RV64ZICOND-LABEL: umulo2.br.i64:
+; RV64ZICOND: # %bb.0: # %entry
+; RV64ZICOND-NEXT: add a1, a0, a0
+; RV64ZICOND-NEXT: bgeu a1, a0, .LBB65_2
+; RV64ZICOND-NEXT: # %bb.1: # %overflow
+; RV64ZICOND-NEXT: li a0, 0
+; RV64ZICOND-NEXT: ret
+; RV64ZICOND-NEXT: .LBB65_2: # %continue
+; RV64ZICOND-NEXT: li a0, 1
+; RV64ZICOND-NEXT: ret
entry:
%t = call {i64, i1} @llvm.umul.with.overflow.i64(i64 %v1, i64 2)
%val = extractvalue {i64, i1} %t, 0
@@ -1226,6 +2483,20 @@ define zeroext i1 @uaddo.i64.constant(i64 %v1, ptr %res) {
; RV64-NEXT: sltu a0, a2, a0
; RV64-NEXT: sd a2, 0(a1)
; RV64-NEXT: ret
+;
+; RV64ZBA-LABEL: uaddo.i64.constant:
+; RV64ZBA: # %bb.0: # %entry
+; RV64ZBA-NEXT: addi a2, a0, 2
+; RV64ZBA-NEXT: sltu a0, a2, a0
+; RV64ZBA-NEXT: sd a2, 0(a1)
+; RV64ZBA-NEXT: ret
+;
+; RV64ZICOND-LABEL: uaddo.i64.constant:
+; RV64ZICOND: # %bb.0: # %entry
+; RV64ZICOND-NEXT: addi a2, a0, 2
+; RV64ZICOND-NEXT: sltu a0, a2, a0
+; RV64ZICOND-NEXT: sd a2, 0(a1)
+; RV64ZICOND-NEXT: ret
entry:
%t = call {i64, i1} @llvm.uadd.with.overflow.i64(i64 %v1, i64 2)
%val = extractvalue {i64, i1} %t, 0
@@ -1242,6 +2513,22 @@ define zeroext i1 @uaddo.i64.constant_2048(i64 %v1, ptr %res) {
; RV64-NEXT: sltu a0, a2, a0
; RV64-NEXT: sd a2, 0(a1)
; RV64-NEXT: ret
+;
+; RV64ZBA-LABEL: uaddo.i64.constant_2048:
+; RV64ZBA: # %bb.0: # %entry
+; RV64ZBA-NEXT: addi a2, a0, 2047
+; RV64ZBA-NEXT: addi a2, a2, 1
+; RV64ZBA-NEXT: sltu a0, a2, a0
+; RV64ZBA-NEXT: sd a2, 0(a1)
+; RV64ZBA-NEXT: ret
+;
+; RV64ZICOND-LABEL: uaddo.i64.constant_2048:
+; RV64ZICOND: # %bb.0: # %entry
+; RV64ZICOND-NEXT: addi a2, a0, 2047
+; RV64ZICOND-NEXT: addi a2, a2, 1
+; RV64ZICOND-NEXT: sltu a0, a2, a0
+; RV64ZICOND-NEXT: sd a2, 0(a1)
+; RV64ZICOND-NEXT: ret
entry:
%t = call {i64, i1} @llvm.uadd.with.overflow.i64(i64 %v1, i64 2048)
%val = extractvalue {i64, i1} %t, 0
@@ -1258,6 +2545,22 @@ define zeroext i1 @uaddo.i64.constant_2049(i64 %v1, ptr %res) {
; RV64-NEXT: sltu a0, a2, a0
; RV64-NEXT: sd a2, 0(a1)
; RV64-NEXT: ret
+;
+; RV64ZBA-LABEL: uaddo.i64.constant_2049:
+; RV64ZBA: # %bb.0: # %entry
+; RV64ZBA-NEXT: addi a2, a0, 2047
+; RV64ZBA-NEXT: addi a2, a2, 2
+; RV64ZBA-NEXT: sltu a0, a2, a0
+; RV64ZBA-NEXT: sd a2, 0(a1)
+; RV64ZBA-NEXT: ret
+;
+; RV64ZICOND-LABEL: uaddo.i64.constant_2049:
+; RV64ZICOND: # %bb.0: # %entry
+; RV64ZICOND-NEXT: addi a2, a0, 2047
+; RV64ZICOND-NEXT: addi a2, a2, 2
+; RV64ZICOND-NEXT: sltu a0, a2, a0
+; RV64ZICOND-NEXT: sd a2, 0(a1)
+; RV64ZICOND-NEXT: ret
entry:
%t = call {i64, i1} @llvm.uadd.with.overflow.i64(i64 %v1, i64 2049)
%val = extractvalue {i64, i1} %t, 0
@@ -1276,6 +2579,26 @@ define i64 @uaddo.i64.constant_setcc_on_overflow_flag(ptr %p) {
; RV64-NEXT: li a0, 0
; RV64-NEXT: .LBB69_2: # %IfNoOverflow
; RV64-NEXT: ret
+;
+; RV64ZBA-LABEL: uaddo.i64.constant_setcc_on_overflow_flag:
+; RV64ZBA: # %bb.0: # %entry
+; RV64ZBA-NEXT: ld a1, 0(a0)
+; RV64ZBA-NEXT: addi a0, a1, 2
+; RV64ZBA-NEXT: bltu a0, a1, .LBB69_2
+; RV64ZBA-NEXT: # %bb.1: # %IfOverflow
+; RV64ZBA-NEXT: li a0, 0
+; RV64ZBA-NEXT: .LBB69_2: # %IfNoOverflow
+; RV64ZBA-NEXT: ret
+;
+; RV64ZICOND-LABEL: uaddo.i64.constant_setcc_on_overflow_flag:
+; RV64ZICOND: # %bb.0: # %entry
+; RV64ZICOND-NEXT: ld a1, 0(a0)
+; RV64ZICOND-NEXT: addi a0, a1, 2
+; RV64ZICOND-NEXT: bltu a0, a1, .LBB69_2
+; RV64ZICOND-NEXT: # %bb.1: # %IfOverflow
+; RV64ZICOND-NEXT: li a0, 0
+; RV64ZICOND-NEXT: .LBB69_2: # %IfNoOverflow
+; RV64ZICOND-NEXT: ret
entry:
%v1 = load i64, ptr %p
%t = call {i64, i1} @llvm.uadd.with.overflow.i64(i64 %v1, i64 2)
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