[llvm] [CodeGen] [ARM] Make RISC-V Init Undef Pass Target Independent and add support for the ARM Architecture. (PR #77770)

[Jack Styles via llvm-commits]

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@@ -152,7 +118,7 @@ bool RISCVInitUndef::handleReg(MachineInstr *MI) {
       continue;
     if (!UseMO.getReg().isVirtual())
       continue;
-    if (!isVectorRegClass(UseMO.getReg()))
+    if (!TII->isVectorRegClass(MRI->getRegClass(UseMO.getReg())))
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Stylie777 wrote:

Check has been deleted. Tests pass locally so functionality is not lost and there are no new issues raised by removing the check. 

https://github.com/llvm/llvm-project/pull/77770