[llvm] [CodeGen] [ARM] Make RISC-V Init Undef Pass Target Independent and add support for the ARM Architecture. (PR #77770)

[Jack Styles via llvm-commits]

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@@ -7,22 +7,21 @@
 //===----------------------------------------------------------------------===//
 //
 // This file implements a function pass that initializes undef vector value to
-// temporary pseudo instruction and remove it in expandpseudo pass to prevent
-// register allocation resulting in a constraint violated result for vector
-// instruction.  It also rewrites the NoReg tied operand back to an
-// IMPLICIT_DEF.
+// temporary pseudo instruction to prevent register allocation resulting in a
+// constraint violated result for vector instructions.  It also rewrites the
+// NoReg tied operand back to an IMPLICIT_DEF.
 //
-// RISC-V vector instruction has register overlapping constraint for certain
-// instructions, and will cause illegal instruction trap if violated, we use
-// early clobber to model this constraint, but it can't prevent register
-// allocator allocated same or overlapped if the input register is undef value,
-// so convert IMPLICIT_DEF to temporary pseudo instruction and remove it later
-// could prevent that happen, it's not best way to resolve this, and it might
+// Certain vector instructions have register overlapping constraints, and
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Stylie777 wrote:

The comment has been update to be more generic, rather than focusing on vector instructions. 

https://github.com/llvm/llvm-project/pull/77770