[llvm] [CodeGen] [ARM] Make RISC-V Init Undef Pass Target Independent and add support for the ARM Architecture. (PR #77770)

[Jack Styles via llvm-commits]

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@@ -327,6 +327,15 @@ class TargetSubtargetInfo : public MCSubtargetInfo {
 
   /// Get the list of MacroFusion predicates.
   virtual std::vector<MacroFusionPredTy> getMacroFusions() const { return {}; };
+
+  // hasVInstructions is used to determine if an architecture supports
+  // vector instructions in relation to Vector CodeGen. By default, it is
+  // assumed that it will not support Vector Instructions, with architecture
+  // specific overrides providing the information where they are implemented.
+  // This was originally used in RISC-V's Init Undef pass but has been moved to
+  // be a virtual function when the pass was refactored to support multiple
+  // architectures.
+  virtual bool hasVInstructions() const { return false; }
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Stylie777 wrote:

This function has been renamed to better reflect its functionality to `supportsInitUndef()`. The RISC V Implementation calls the `hasVInstructions()` function to functionality is the same for the architecture. 

I have also added a check for AdvSIMD instructions on Arm. 

https://github.com/llvm/llvm-project/pull/77770