[llvm] [GISEL][RISCV] IRTranslator for scalable vector load (PR #80006)

[Michael Maitland via llvm-commits]

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@@ -0,0 +1,7 @@
+; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=+v -global-isel -stop-after=irtranslator -verify-machineinstrs < %s | FileCheck  -check-prefixes=RV32I %s
+
+define void @vload_vint8m1(ptr %pa) {
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michaelmaitland wrote:

I think we should have tests that include the align argument and tests that do not include the align argument.

We probably need to add support for both aligned and unaligned load/store. It is probably okay to start off with only worrying about aligned loads/stores. I would have thought that `align 8` and `align 4` is aligned on rv32 and `align 8` is aligned on rv64, but `llvm/test/CodeGen/RISCV/rvv/unaligned-loads-stores.ll::aligned_load_nxv1i32_a4` seems to imply that `align 4` is also aligned on rv64 -- @topperc are you able eto clarify this?

https://github.com/llvm/llvm-project/pull/80006