[llvm] [GISEL][RISCV] IRTranslator for scalable vector load (PR #80006)

[Craig Topper via llvm-commits]

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@@ -0,0 +1,7 @@
+; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=+v -global-isel -stop-after=irtranslator -verify-machineinstrs < %s | FileCheck  -check-prefixes=RV32I %s
+
+define void @vload_vint8m1(ptr %pa) {
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topperc wrote:

The alignment is relative to EEW not XLen.

> If an element accessed by a vector memory instruction is not naturally aligned to the size of the element, either the element is transferred successfully or an address misaligned exception is raised on that element.

https://github.com/llvm/llvm-project/pull/80006